In this paper, a discrete-time convergence theorem for continuous-state Hopfield networks with self-interaction neurons is proposed. This theorem differs from the previous work by Wang in that the original updating rule is maintained while the network is still guaranteed to monotonically decrease to a stable state. The relationship between the parameters in a typical class of energy functions is also investigated, and consequently a "guided trial-and-error" technique is proposed to determine the parameter values. The third problem discussed in this paper is the post-processing of outputs, which turns out to be rather important even though it never attracts enough attention. The effectiveness of all the theorems and post-processing methods proposed in this paper is demonstrated by a large number of computer simulations on the assignment problem and the N-queen problem of different sizes.

This paper describes how the symmetry of a three-phase circuit prevents the symmetric modes of several subharmonic oscillations. First, we make mathematically it clear that the generation of symmetrical 1/3l-subharmonic oscillations (l=1,2,) are impossible in the three-phase circuit. As far as 1/(3l+1)-subharmonic oscillations (l=1,2,) and 1/(3l+2)-subharmonic oscillations (l=0,1,) are concerned, the former in negative-phase sequence and the latter in positive-phase sequence are shown to be impossible. Further, in order to confirm the above results, we apply the method of interval analysis to the circuit equations and obtain all steady state solutions with unsymmetric modes.

The reflection signal in the inverse synthetic aperture radar is measured in the polar coordinate defined by the object rotation angle and the frequency. The reconstruction of fixed scene images requires the coordinate transformation of the polar format data into the rectangular spatial frequency domain, which is then processed by the inverse Fourier transform. In this paper a fast and flexible method of coordinate transformation based on the nearest neighbor interpolation utilizing the Delauney triangulation is at first presented. Then, the induced errors in the transformed rectangular spatial frequency data and the resultant fixed scene images are investigated by simulation under the uniform plane wave transmit-receive mode over the swept frequency 120-160 GHz, and the results which demonstrate the validity of the current coordinate transformation are presented.

We present iterative round-robin matching for an input and output buffered switch with multiple switching planes. The suggested algorithm is based on iSLIP and consists of request, grant and accept steps. The pointer update scheme of iSLIP is altered in the suggested algorithm to enhance the switch performance. Simulation results under Bernoulli traffic show the suggested algorithm is more appropriate than iSLIP for cell scheduling of input and output buffered switches.

In this paper, genetic algorithms is employed to determine the shape of a conducting cylinder buried in a half-space. Assume that a conducting cylinder of unknown shape is buried in one half-space and scatters the field incident from another half-space where the scattered filed is measured. Based on the boundary condition and the measured scattered field, a set of nonlinear integral equations is derived and the imaging problem is reformulated into an optimization problem. The genetic algorithm is then employed to find out the nearly global extreme solution of the object function such that the shape of the conducting scatterer can be suitably reconstructed. In our study, even when the initial guess is far away from the exact one, the genetic algorithm can avoid the local extremes and converge to a reasonably good solution. In such cases, the gradient-based methods often get stuck in local extremes. Numerical results are presented and good reconstruction is obtained both with and without the additive Gaussian noise.

In this paper, we study nonblocking supervisory control of discrete event systems under partial observation. We introduce a weak normality condition defined in terms of a modified natural projection map. The weak normality condition is weaker than the original one and stronger than the observability condition. Moreover, it is preserved under union. Given a marked language specification, we present a procedure for computing the supremal sublanguage which satisfies Lm(G)-closure, controllability, and weak normality. There exists a nonblocking supervisor for this supremal sublanguage. Such a supervisor is more permissive than the one which achieves the supremal Lm(G)-closed, controllable, and normal sublanguage.

A multiport representation of the step junction of two circular dielectric waveguides of different size is given. Continuous spectral modes of the circular dielectric waveguide are discretized at a terminal plane by means of expressing their mode amplitudes in the form of infinite series of orthonormal Gaussian Laguerre function. Applying the mode matching technique, a multiport representation of the step junction is derived. Numerical examples are given where the results are tested for the conservation of power. Also the numerical results are compared with those from Marcuse's approximate methods.

As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.

We present a simple cell scheduling algorithm for an input buffered switch. The suggested algorithm is based on iSLIP and consists of request, grant and accept steps. The pointer update scheme of iSLIP is simplified in the suggested algorithm. By virtue of the new update scheme, the performance of the suggested algorithm is better than that of iSLIP with one iteration. Using computer simulations under a uniform traffic, we show the suggested algorithm is more appropriate than iSLIP for scheduling of an input buffered switch with multiple service classes.

In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.

External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.

Spatiotemporal chaos in a multidomain regime in a Gunn-effect device is numerically investigated as an example of collective domain oscillations under global constraints. The dynamics of carrier densities are computed using a set of model partial differential equations. Numerical results reveal some distinctive and chaotic clustering features caused by the global coupling and boundary effects. The chaotic regime is then characterized in terms of a Lyapunov spectrum and Lyapunov dimension, the latter increasing with the size of the system.

This paper proposes a heuristic algorithm which, given a basis of a subspace of the space of cuspforms of weight 2 for 0(N) which is invariant for the action of the Hecke operators, tests whether the subspace corresponds to a quotient A of the jacobian of the modular curve X0(N) such that A is the jacobian of a curve C. Moreover, equations for such a curve C are computed which make the quotient suitable for applications in cryptography. One advantage of using such quotients of modular jacobians is that fast methods are known for finding their number of points over finite fields.

The next generation of wireless networks must provide sufficient resources to support a broader range of services beyond the traditional voice-only services provided in current wireless systems. For this, packet scheduling is the most critical function involved in the provision of individual bandwidth, and delay guarantee to meet the required qualities of service (QoS) for the switched sessions. In this paper we introduce the concept of system capacity in the multi-code CDMA system and evaluate the system performance constrained by the required SNRth and other QoS factors. The CAC algorithm is proposed to administer the requests. Moreover, the enforcer, scheduler and shaper are proposed to maintain the required QoS. The system performance including blocking probability, mean delay and bandwidth utilization in the BS egress are evaluated and compared under different traffic loadings.

Power supply rejection ratio (PSRR) characteristics of a switched capacitor filter (SCF) is improved when using an equal level diagram design of a leapfrog type filter. By using this design method, it is shown that PSRR of a SCF measured is improved about 20 dB.

Multisignature scheme realizes that plural users generate the signature on a message, and that the signature is verified. Various studies on multisignature have been proposed. They are classified into two types: RSA-based multisignature, and discrete logarithm problem (DLP) based multisignature, all of which assume that a message is fixed beforehand. In a sense, these schemes do not have a feature of message flexibility. Furthermore all schemes which satisfy with order verifiability designate order of signers beforehand. Therefore these protocols have a feature of order verifiability but not order flexibility. For a practical purpose of circulating messages soundly through Internet, a multisignature scheme with message flexibility, order flexibility and order verifiability should be required. However, unfortunately, all previous multisignature do not realize these features. In this paper, we propose a general model of multisignature schemes with flexibility and verifiability. We also present two practical schemes based on DLP based message recover signature and RSA signature, respectively.

WFQ (Weighted Fair Queueing) is an ideal scheduling algorithm in terms of delay and fairness. However, timestamp computation complexity makes the implementation difficult. In this paper we propose an efficient and simple fair queueing algorithm, called Emulated Weighted Fair Queueing (EWFQ), which has O(1) complexity for the virtual time computation while it almost perfectly emulates the delay and fairness properties of WFQ. The key idea of EWFQ is that it calibrates the system virtual time only at the end of each packet transmission, while it calculates the system virtual time for a newly arrived packet by employing a linear approximation. By doing so, EWFQ has a rate-proportional property. EWFQ can be implemented in a router for supporting the differential and integrated services.

In this report we demonstrate the characteristics of the opt-electrical transducer that is newly designed for a fiber-optic wireless access system. This transducer consists of a monolithic microwave integrated circuit (MMIC) oscillator whose oscillation frequency is over 30 GHz. The active element of the oscillator is an InAlAs/InGaAs high electron mobility transistor (HEMT). The shift of frequency is observed when we illuminate 1.55 µm wavelength light onto the HEMT area. The size of the frequency shift is -150 MHz/mW, and it does not change as a function of gate bias conditions. We also confirm that the oscillator is able to respond with an optical signal of 500 MHz, which is sufficiently fast to achieve 156 Mbit/s communication. If this transducer is introduced into the base station (BS) of a fiber-optic wireless access system, a high-speed optical modulator no longer has to be incorporated into the control station. As a result, the configuration of the system becomes simpler than that of Radio on Fiber. We constructed a system that adopts the frequency shift keying technique with application of the transducer into the BS and then performed a transmission experiment at 5 Mbit/s. The demodulated data is sufficiently clear to distinguish high from low. Therefore, we can put forth that the fabricated transducer is a promising candidate as a device for the BS of a fiber-optic millimeter-wave wireless access system.

A periodic approach introduced previously is applied to the TM wave scattering from a finite periodic surface. A mathematical relation is proposed to estimate the scattering amplitude from the diffraction amplitude for the periodic surface, where the periodic surface is defined as a superposition of surface profiles generated by displacing the finite periodic surface by every integer multiple of the period . From numerical examples, it is concluded that the scattering cross section for the finite periodic surface can be well estimated from the diffraction amplitude for a sufficiently large .