In this paper, an efficient equivalence checking method for two C descriptions is described. The equivalence of two C descriptions is proved by symbolic simulation. Symbolic simulation used in this paper can prove the equivalence of all of the variables in the descriptions. However, it takes long time to verify the equivalence of all of the variables if large descriptions are given. Therefore, in order to improve the verification, our method identifies textual differences between descriptions. The identified textual differences are used to reduce the number of equivalence checkings among variables. The proposed method has been implemented in C language and evaluated with several C descriptions.

As an enhancement of the state-of-the-art solutions, a high-throughput architecture of a decoder for structured LDPC codes is presented in this paper. Thanks to the peculiar code definition and to the envisaged architecture featuring memory paging, the decoder is very flexible, and the support of different code rates is achieved with no significant hardware overhead. A top-down design flow of a real decoder is reported, starting from the analysis of the system performance in finite-precision arithmetic, up to the VLSI implementation details of the elementary modules. The synthesis of the whole decoder on 0.18µm standard cells CMOS technology showed remarkable performances: small implementation loss (0.2dB down to BER = 10-8), low latency (less than 6.0µs), high useful throughput (up to 940Mbps) and low complexity (about 375 Kgates).

In conventional OFDM systems, the effect of inter-block-interference (IBI) can be completely removed by inserting sufficient redundant symbols between successive transmission blocks. In this paper, based on the reformulated received block symbols of the discrete multirate filterbanks model, a new transceiver model for the cyclic prefix (CP) OFDM systems is proposed, associated with the oblique projector technique (view as the pre-processor for achieving IBI-free). Consequently, a novel ISI-free receiver with the zero-order FIR zero-forcing (ZF) filterbanks equalizer can be devised, under noise-free environment. For performance comparison the bit-error-rate (BER) is investigated for the cases of noisy and noise-free channels. In all cases, viz., the length of CP is shorter or longer than the order of the channel impulse response, we show that the same BER performance compared with the one suggested in [3] can be achieved, under the same assumptions and conditions. Since a simple cascade configuration of the IBI cancellation using the oblique projector followed by the ISI cancellation using the zero-order FIR ZF filterbanks equalizer can be realized for OFDM systems with sufficient or insufficient CP, the complexity of transceiver design can be reduced.

Locality in high frequency diffraction is embodied in the Method of Moments (MoM) in view of the method of stationary phase. Local-domain basis functions accompanied with the phase detour, which are not entire domain but are much larger than the segment length in the usual MoM, are newly introduced to enhance the cancellation of mutual coupling over the local-domain; the off-diagonal elements in resultant reaction matrix evanesce rapidly. The Fresnel zone threshold is proposed for simple and effective truncation of the matrix into the sparse band matrix. Numerical examples for the 2-D strip and the 2-D corner reflector demonstrate the feasibility as well as difficulties of the concept; the way mitigating computational load of the MoM in high frequency problems is suggested.

NAT-PT and DSTM are becoming more widespread as de-facto standards for IPv6 dominant network deployment. But few researchers have empirically evaluated their performance aspects. In this paper, we compared the performance of NAT-PT and DSTM with IPv4-only and IPv6-only networks on user applications using metrics such as throughput, CPU utilization, round-trip time, and connect/request/response transaction rate.

Low-density parity-check (LDPC) codes are one of the most promising next-generation error-correcting codes. For practical use, efficient methods for encoding of LDPC codes are needed and have to be studied. However, it seems that no general encoding methods suitable for hardware implementation have been proposed so far and for randomly constructed LDPC codes there have been no other methods than the simple one using generator matrices. In this paper we show that some classes of quasi-cyclic LDPC codes based on circulant permutation matrices, specifically LDPC codes based on array codes and a special class of Sridhara-Fuja-Tanner codes and Fossorier codes can be encoded by division circuits as cyclic codes, which are very easy to implement. We also show some properties of these codes.

This paper tackles the problem of detecting a random signal embedded in additive white noise. Although the likelihood ratio test (LRT) is the well-known optimum detector for this problem, it may not be easily realized in applications such as radar, sonar, seismic, digital communications, speech analysis and automatic fault detection in machinery, for which suboptimal quadratic detectors have been extensively employed. In this paper, the relationships between four suboptimal quadratic detection schemes, namely, the energy, matched subspace, maximum deflection ratio as well as spectrum matching detectors, and the LRT are studied. In particular, we show that each of those suboptimal detectors can approach the optimal LRT under certain operating conditions. These results are verified via Monte Carlo simulations.

In the letter we extend our previous work, which applies genetic programming to passive filter synthesis tasks. The extended method deals with the tolerance design considerations. Experimental results show that our method can effectively generate filters which outperform those generated by traditional methods. In addition, it provides filter designers with an effective CAD tool to manage the trade-off between manufacturing yield and circuit cost.

This paper presents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528 MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.

This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The technique utilizes a commercially available logic synthesis tool that has been well established for static CMOS logic design, where an intermediate library is devised for logic synthesis likely as static CMOS, and then a resulting synthesized circuit is translated automatically into ASDDL implementation at the gate-level logic schematic level as well as at the physical-layout level. A design example of an ASDDL 16-bit multiplier synthesized in a 0.18-µm CMOS technology shows an operation delay time of 1.82 nsec, which is a 32% improvement over a static CMOS design with a static logic standard-cell library that is finely tuned for energy-delay products. Design with the 16-bit multiplier led to a design time for an ASDDL based dynamic digital circuit 300 times shorter than that using a fully handcrafted design, and comparable with a static CMOS design.

Gossip-based reliable broadcast protocols with reasonably weak reliability properties scale well to large groups and degrade system performance gracefully even if node failure or message loss rates increase compared with traditional protocols. However, although many distributed applications require highly steady performance only by allowing causality to be used asynchronously, there is no existing gossip-based protocol offering causally ordered delivery property more lightweight than totally ordered delivery one. This paper presents an application-level broadcast algorithm to guarantee causally-ordered delivery semantics based on peer to peer interaction models for scalability, reasonable reliability and stable throughput. Processes propagate each message with a vector time stamp much like the spread of rumor in society for a fixed number of rounds. Upon receipt of these messages, correct processes immediately deliver the corresponding messages to the application layers in a causal order. Simulation results show that the proposed algorithm outperforms the existing ones in terms of delivery throughput.

Pattern extraction is an indispensable step in bare printed circuit board (PCB) inspection and plays an important role in automatic inspection system design. A good approach for pattern definition and extraction will make the following PCB diagnosis easy and efficient. The window-based technique has great potential in PCB patterns extraction due to its simplicity. The conventional window-based pattern extraction methods, such as Small Seeds Window Extraction method (SSWE) and Large Seeds Window Extraction method (LSWE), have the problems of losing some useful copper traces and splitting slanted-lines into too many small similar windows. These methods introduce the difficulty and computation intensive in automatic inspection. In this paper, a novel method called Contour Based Window Extraction (CBWE) algorithm is proposed for improvement. In comparison with both SSWE and LSWE methods, the CBWE algorithm has several advantages in application. Firstly, all traces can be segmented and enclosed by a valid window. Secondly, the type of the entire horizontal or vertical line of copper trace is preserved. Thirdly, the number of the valid windows is less than that extracted by SSWE and LSWE. From the experimental results, the proposed CBWE algorithm is demonstrated to be very effective in basic pattern extraction from bare PCB image analysis.

Although the multiuser detection scheme based on Kalman filtering (K-MUD) proposed by Zhang and Wei, is referred to as a "blind" algorithm, in fact it is not really blind because it is conditioned on perfect knowledge of system parameter, power of the desired user. This paper derives an algorithm to estimate the power of the user of interest, and proposes a completely blind multiuser detection. Computer simulations show that the proposed parameter estimation scheme obtains excellent effect, and that the new detection scheme has nearly the same performance as the K-MUD, there is only slight degradation at very low input signal-to-interference ratios (SIR).

This paper introduces a new approach to realize a multi-state operation on the microwave isolator using ferrite edge-mode. The voltage control of total transmission on the isolator is realized. The operation is based on the unique property of ferrite edge-mode and the variable resistance of PIN diodes. On the isolator, the frequency response is investigated both experimentally and numerically. The numerical analysis is performed by the FDTD method. Both numerical and experimental results have shown that the transmission between two ports can be totally controlled by the applied voltage for the diodes. The experimental results indicate that the transmission direction can be controlled at 11 GHz, and the isolation ratio can be controlled for more than 30 dB.

An inverse scattering problem of estimating the surface impedance for an inhomogeneous half-space is investigated. By virtue of the fact that the far field representation contains the spectral function of the scattered field, complex values of the function are estimated from a set of absolute values of the far field. An approximate function for the spectral function is reconstructed from the estimated complex values by the least-squares sense. The surface impedance is estimated through calculating the field on the surface of the half-space expressed by the inverse Fourier transform. Numerical examples are given and the accuracy of the estimation is discussed.

The relative permittivity and permeability are discontinuous at the grating profile, and the electric and magnetic flux densities are continuous. As for the method of analysis for scattering waves by surface relief gratings placed in conical mounting, the spatial harmonic expansion approach of the flux densities are formulated in detail and the validity of the approach is shown numerically. The present method is effective for uniform regions such as air and substrate in addition to grating layer. The matrix formulations are introduced by using numerical calculations of the matrix eigenvalue problem in the grating region and analytical solutions separated for TE and TM waves in the uniform region are described. Some numerical examples for linearly and circularly polarized incidence show the usefulness of the flux densities expansion approach.

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

A design of a linearly-polarized non-resonant waveguide broad-wall transverse slot linear array with suppressed grating lobes is presented. Each unit element in the array consists of a transverse slot, an inductive post and a parasitic dipole-pair at a height of half of the free space wavelength. It is designed as an isolated unit without considering mutual coupling by using the Method of Moments (MoM) for radiation suppression in grating beam direction and reflection cancellation at the input. The elements thus designed are used in a travelling wave array environment. It is predicted that the reflection is less than -20 dB at 11.95 GHz while the grating lobes are suppressed by more than 15 dB. The design and the characteristics of the array are confirmed by measurements.

Signal detectors generally utilize nonlinear statistics of an original observation rather than the original observation as it is. The sign statistic, a typical example of the nonlinear statistics, is the sign information of an observation and the sign detector relies only on the sign statistic. Since either detector might be of a better performance depending on the situation, it is quite important to determine which is the best performer among the detectors, based on the given situational information about noise and signal strength. In this letter, a qualitative analysis is presented that the correlation coefficients between the statistics and original observation can be used to predict the asymptotic performance of a detector utilizing one of the statistics, relative to the other detectors.

Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity reduction, we concentrate on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 1616-bit multiplier by 34% and 29% on peak and by 10% and 7% on average with area overhead of 15% and 4%, respectively, while maintaining the performance of traditional multiplier.