To achieve both of a high peak performance and low average power characteristics, frequency-voltage cooperative control processor has been proposed. The processor schedules its operating frequency according to the required computation power. Its operating voltage or body bias voltage is adequately modulated simultaneously to effectively cut down either switching current or leakage current, and it results in reduction of total power dissipation of the processor. Since a frequency-voltage cooperative control processor has two or more operating frequencies, there are countless scheduling methods exist to realize a certain number of cycles by deadline time. This proposition is frequently appears in a hard real-time system. This paper proves two important theorems, which give the power-minimum frequency scheduling method for any types of frequency-voltage cooperative control processor, such as Vdd-control type, Vth-control type and Vdd-Vth-control type processors.

In this paper a straight-forward approach to extract the equivalent loop-gain of a continuous time Delta-Sigma modulator with an arbitrary DAC waveform in z-domain is presented. In this approach the arbitrary DAC waveform is approximated by the infinite number of rectangular pulse shapes. Then simply using the transformations available in literatures for a rectangular DAC pulse shape and applying superposition on each rectangular pulse shape, the loop-gain of the system is derived in z-domain.

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

This paper describes a novel engineering change order (ECO) design method for large-scale, high performance LSIs, based on a patchwork-like partitioning technique. In conventional design methods, even when only small changes are made to the design after the placement and routing process, a whole re-layout must be done, and this is very time consuming. Using the proposed method, we can partition the design into several parts after logic synthesis. When design changes occur in HDL, only the parts related to the changes need to be redesigned. The netlist for the changed design remains almost the same as the original, except for the small changed parts. For partitioning, we used multiple-fan-out-points as partition borders. An experimental evaluation of our method showed that when a small change was made in the RTL description, the revised circuit part had only about 87 gates on average. This greatly reduces the re-layout time required for implementing an ECO. In actual commercial designs in which several design changes are required, it takes only one day to redesign.

In this paper, an efficient equivalence checking method for two C descriptions is described. The equivalence of two C descriptions is proved by symbolic simulation. Symbolic simulation used in this paper can prove the equivalence of all of the variables in the descriptions. However, it takes long time to verify the equivalence of all of the variables if large descriptions are given. Therefore, in order to improve the verification, our method identifies textual differences between descriptions. The identified textual differences are used to reduce the number of equivalence checkings among variables. The proposed method has been implemented in C language and evaluated with several C descriptions.

A systematic method is introduced to the computational synthesis of CMOS voltage followers (VFs). The method is divided in three steps: generation of the small-signal circuitry by selection of nullators to model the behavior of a VF, and addition of norators to form nullator-norator joined-pairs; generation of the bias circuitry by addition of ideal biases according to the properties of nullators and norators; and synthesis of the joined-pairs by MOSFETs, and of the current-biases by CMOS current mirrors. It is shown that the proposed synthesis method has the capability to generate already known and new CMOS VF topologies.

This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.

The Reed-Solomon code is a versatile channel code pervasively used for communication and storage systems. The bit-serial Reed-Solomon encoder has a simple structure, although it is somewhat difficult to understand the algorithm without considerable theoretical background. Some professionals and students, not able to understand the algorithm thoroughly, might need to implement the bit-serial encoder for themselves. In this letter, a step-by-step method is presented for the implementation of the bit-serial encoder even without understanding the internal algorithm, which would be helpful for VHDL, DSP, and simulation programming.

In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).

We propose utilizing subband-based blind source separation (BSS) for convolutive mixtures of speech. This is motivated by the drawback of frequency-domain BSS, i.e., when a long frame with a fixed long frame-shift is used to cover reverberation, the number of samples in each frequency decreases and the separation performance is degraded. In subband BSS, (1) by using a moderate number of subbands, a sufficient number of samples can be held in each subband, and (2) by using FIR filters in each subband, we can manage long reverberation. We confirm that subband BSS achieves better performance than frequency-domain BSS. Moreover, subband BSS allows us to select a separation method suited to each subband. Using this advantage, we propose efficient separation procedures that consider the frequency characteristics of room reverberation and speech signals (3) by using longer unmixing filters in low frequency bands and (4) by adopting an overlap-blockshift in BSS's batch adaptation in low frequency bands. Consequently, frequency-dependent subband processing is successfully realized with the proposed subband BSS.

Fixed polarity Reed-Muller expressions (FPRMs) exhibit several useful properties that make them suitable for many practical applications. This paper presents an exact minimization algorithm for FPRMs for incompletely specified functions. For an n-variable function with α unspecified minterms there are 2n+α distinct FPRMs, and a minimum FPRM is one with the fewest product terms. To find a minimum FPRM the algorithm requires to determine an assignment of the incompletely specified minterms. This is accomplished by using the concept of integer-valued functions in conjunction with an extended truth vector and a weight vector. The vectors help formulate the problem as an assignment of the variables of integer-valued functions, which are then efficiently manipulated by using multi-terminal binary decision diagrams for finding an assignment of the unspecified minterms. The effectiveness of the algorithm is demonstrated through experimental results for code converters, adders, and randomly generated functions.

In this Letter, linear least squares (LLS) techniques for phase estimation of real sinusoidal signals with known or unknown amplitudes are studied. It is proved that the asymptotic performance of the LLS approach attains Cramér-Rao lower bound. For the case of a single tone, a novel LLS algorithm with unit-norm constraint is derived. Simulation results are also included for algorithm evaluation.

There is "Processing speed improvement of the automatic fare collection gate (AFC gate)" as one of the important problems to correspond to the passengers getting on and off in high density transportation at the peak. On the other hand, reliability is indispensable to handle the ticket that is the note. Therefore, the ticket system that has both high-speed processing and high reliability is necessary and indispensable. For the passenger's convenience improvement and maintenance cost reduction, wireless IC card ticket system is hoped. However, the high-speed processing and the high reliability are ambivalent at this system because of wireless communications between an IC card and an AFC gate; the faster the AFC gate processes the ticket, the poorer the reliability gets. In this thesis, it proposes the autonomous decentralized processing technology to meet high-speed processing in wireless IC ticket system and the requirement of high reliability. "IC card" "AFC" and "Central server" are assumed to be an autonomous system. It proposes "Decentralized algorithm of the fare calculation by IC card and the AFC" to achieve high-speed processing. Moreover, "Autonomous, decentralized consistency technology" in each subsystem is shown for high-reliability. In addition, to make these the effective one, "Wireless communication area enhancing technology (touch & going method)" and "Command system for the data high speed processing" are shown. These technologies are introduced into the Suica system of East Japan Railway and the effectiveness has been proven.

Although the multiuser detection scheme based on Kalman filtering (K-MUD) proposed by Zhang and Wei, is referred to as a "blind" algorithm, in fact it is not really blind because it is conditioned on perfect knowledge of system parameter, power of the desired user. This paper derives an algorithm to estimate the power of the user of interest, and proposes a completely blind multiuser detection. Computer simulations show that the proposed parameter estimation scheme obtains excellent effect, and that the new detection scheme has nearly the same performance as the K-MUD, there is only slight degradation at very low input signal-to-interference ratios (SIR).

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

In OFDM systems, employing a cyclic prefix (CP) as the guard interval is a simple way to combat the inter-symbol interference (ISI) and the inter-carrier interference (ICI), however it reduces the transmission efficiency of the system, especially for some channels with a very long delay spread. In this paper, we consider the OFDM system with insufficient CP, much more efficient than conventional OFDM systems. First, we present the system mathematical model and give the ISI and ICI analysis. Then the signal-to-interference power ratio (SIR) performance is presented. To reduce the ISI and ICI due to the insufficient CP, we develop a minimum-mean-square-error decision feedback equalizer (MMSE_DFE). Based on the MMSE criterion, the optimum feedforward and feedback filter coefficients are derived. For time-varying channel, to avoid brute force matrix inversion in conventional schemes, we propose an adaptive LMS based solution to update the filtering coefficients by tracing the channel variation. Since the high complexity of MMSE_DFE, a reduced complexity scheme, ordered successive partial interference cancellation DFE (OSPIC_DFE), is developed. From the performance comparison between the MMSE_DFE and the OSPIC_DFE, we see that the latter is very near to the former. Finally the simulation shows these proposed methods are highly effective in combating ISI and ICI with low complexity.

An efficient void filling (VF) algorithm is proposed for wavelength division multiplexing (WDM) optical packet switches (OPSes) handling variable-packet-length self-similar traffic. The computation complexity of the proposed algorithm is extremely low. We further compare the switching performance of the proposed algorithm with that of the conventional one. We demonstrate that the proposed algorithm offers significantly lower computation complexity with adequate performance.

In this paper, a multiple-pulse signaling format for M-ary equicorrelated modulation (ECM) is proposed to enable the noncoherent detection on a multiple-symbol basis. Several time-limited and band-limited basis waveform sets are designed to embody the multiple-pulse ECM signals and explored to determine the spectral performance characteristics. Based on the maximum-likelihood decision principle, a block receiver is developed for noncoherently demodulating multiple-pulse ECM signals on additive white Gaussian noise channels. Tight upper and approximate bounds are derived and verified by simulation to evaluate the bit and symbol error probability characteristics of the developed ECM block receiver. It is analytically shown that the noncoherent M-ary ECM block receiver with a small-sized blocklength offers comparable performance to the ideal coherent M-ary simplex receiver when the pairwise signal correlation is appropriately chosen. In particular, the proposed noncoherent nonbinary simplex modulation is found to strongly outperform the conventional noncoherent nonbinary orthogonal modulation in terms of both power and spectral efficiencies.

We propose a multiple dwell serial search (MDSS) code acquisition for optical code-division multiple-access (O-CDMA) systems and theoretically analyze its performance. The search/lock strategy (SLS) is used as verification scheme for the multiple dwell detector. The operation of SLS is modeled by finite Markov chain to analyze the performance of the proposed system. Effect of system parameters, such as number of users, threshold and mean photon count per chip, on the performance of the proposed system is investigated. The theoretical result shows that the performance of the proposed system is less sensitive to parameter settings than the conventional single dwell serial search (SDSS) code acquisition system is. In addition, the proposed MDSS code acquisition system offers shorter mean acquisition time than that of conventional SDSS system.