In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are 6 kHz of carrier frequency offset, 110 ppm of symbol rate offset, and -82 dBc carrier phase-jitter at 10 kHz away from the nominal carrier frequency.

This paper describes a method to represent m output functions using shared multi-terminal binary decision diagrams (SMTBDDs). The SMTBDD(k) consists of multi-terminal binary decision diagrams (MTBDDs), where each MTBDD represents k output functions. An SMTBDD(k) is the generalization of shared binary decision diagrams (SBDDs) and MTBDDs: for k=1, it is an SBDD, and for k=m, it is an MTBDD. The size of a BDD is the total number of nodes. The features of SMTBDD(k)s are: 1) they are often smaller than SBDDs or MTBDDs; and 2) they evaluate k outputs simultaneously. We also propose an algorithm for grouping output functions to reduce the size of SMTBDD(k)s. Experimental results show the compactness of SMTBDD(k)s. An SMTBDDmin denotes the smaller SMTBDD which is either an SMTBDD(2) or an SMTBDD(3) with fewer nodes. The average relative sizes for SBDDs, MTBDDs, and SMTBDDs are 1. 00, 152. 73, and 0. 80, respectively.

In the spatial network method (SNM) for the vector potential, both the current continuity law including polarization vector and the conservation law of generalized momentum including vector potential field can introduce simpler expressions for dispersive property than that by the electromagnetic field variables. But for the anisotropic medium conditions, the conventional expanded node expression has some difficulties in treating the coupling mechanism among field variables. On the other hand, in the condensed node expression, in which all field components exist at each node, every connections among field components can be simply formulated. In this paper, after proposing the condensed node spatial network method for the vector potential, the advantage of the method such as performing the simplified formulation by utilization of both the vector potential and the condensed node expressions is presented for the magnetized plasma which has the gyro-anisotropy. The validity of the computation is shown by some examples such as Faraday rotation.

MOSFETs with sub-0.1 µm gate length were fabricated, and their low temperature operation was investigated. The drain current for drain voltage of 2 V increased monotonously as temperature was lowered to 15 K without an influence of the freeze-out effect. Moreover, the increase in the drain current was enhanced by the gate length reduction. The hot-carrier effect at low temperature was also investigated. Impact-ionization decreased as temperature was lowered under the condition of drain voltage 2 V. The decreasing ratio was enhanced as gate length became shorter. We consider this phenomenon is attributed to the non-steady-stationary effect. As a result, device degradation by DC stressing was reduced at 77 K in comparison with room temperature. In the case of 0.1 µm MOSFET, drain current was not degraded in condition of DC stress with gate- and drain-voltage was 1.5 V.

This paper presents a new compound constructive algorithm of neural networks whereby the fuzzy logic technique is explored as an efficient learning algorithm to implement an optimal network construction from an initial simple 3-layer network while the genetic algorithm is used to help design an improved network by evolutions. Numerical simulations on artificial life demonstrate that compared with the existing network design algorithms such as the constructive algorithms, the pruning algorithms and the fixed, static architecture algorithm, the present algorithm, called FuzGa, is efficient in both time complexity and network performance. The improved time complexity comes from the sufficiently small 3 layer design of neural networks and the genetic algorithm adopted partly because the relatively small number of layers facilitates an utilization of an efficient steepest descent method in narrowing down the solution space of fuzzy logic and partly because trappings into local minima can be avoided by genetic algorithm, contributing to considerable saving in time in the processing of network learning and connection. Compared with 54. 8 minutes of MLPs with 65 hidden neurons, 63. 1 minutes of FlexNet or 96. 0 minutes of Pruning, our simulation results on artificial life show that the CPU time of the present method reaching the target fitness value of 100 food elements eaten for the present FuzGa has improved to 42. 3 minutes by SUN's SPARCstation-10 of SuperSPARC 40 MHz machine for example. The role of hidden neurons is elucidated in improving the performance level of the neural networks of the various schemes developed for artificial life applications. The effect of population size on the performance level of the present FuzGa is also elucidated.

This paper discusses the experimental evaluation of the knowledge-based program understander ALPUS and methods of program normalization based on the evaluation to improve the flexibility of the system performance. ALPUS comprehends students' buggy Pascal programs using four kinds of programming knowledge, detects logical bugs, infers user's intentions and gives advice for fixing bugs. By means of the combination of the pattern matching technique and the HPG-based formalism of programming knowledge in addition to program normalization high performance of comprehension has been achieved for relatively complex programs such as Quicksort programs. The experimental evaluation told that program normalization would solve some 55% of unsucceeded student programs. Program normalization has contributed both in decreasing the number of knowledge patterns and increasing the flexibility. This paper proposes a five-step normalization procedure which works well in an experimental situation.

In this paper we have introduced a new method for signature pattern recognition, taking advantage of some image moment transformations combined with fuzzy logic approach. For this purpose first we tried to model the noise embedded in signature patterns inherently and separate it from environmental effects. Based on the first step results, we have performed a mapping into the unit circle using the error least mean square (LMS) error criterion, to get ride of the variations caused by shifting or scaling. Then we derived some orientation invariant moments introduced in former reports and studied their statistical properties in our special input space. Later we defined a fuzzy complex space and also a fuzzy complex similarity measure in this space and constructed a new training algorithm based on fuzzy learning vector quantization (FLVQ) method. A comparison method has also been proposed so that any input pattern could be compared to the learned prototypes through the pre-defined fuzzy similarity measure. Each set of the above image moments were used by the fuzzy classifier separately and the mis-classifications were detected as a measure of error magnitude. The efficiency of the proposed FLVQ model has been numerically shown compared to the conventional FLVQs reported so far. Finally some satisfactory results are derived and also a comparison is made between the above considered image transformations.

In this paper, we will discuss circuit minimization techniques based on the multiple output capability of FPGA blocks. Since previous methods only consider two independent output functions, we will discuss a more complicated case when the two functions are mutually related. We also discuss a method to maximize flexibility of a specified cell output in the given FPGA block. If a set of possible functions for a cell which will not change the FPGA output function is large, we call that the flexibility of this cell is high. The concept of Sets of Pairs of Functions to be Distinguished (SPFDs) introduced by Yamashita et al. is a powerful tool to minimize a given FPGA circuits. In this paper, an extension of the concept, Priority based SPFDs (PSPFDs) is introduced to maximize the flexibility of output functions realized by such internal cells. By using PSPFDs for our new method, we can utilize the multiple output capability very well. Combination with the previous methods with PSPFDs is also shown to be important. We have implemented these methods and applied them to MCNC benchmarks mapped into 5-variable function blocks. To make a comparison with other methods, we have implemented methods using well-known merging algorithms utilizing the same multiple output capability. Experimental results show that our methods can reduce the number of blocks in the initial circuits by 40% on average. This reduction ratio is 16% higher than that of previous methods.

Hardware software codesign using various hardware and software implementation possibilities requires a cosimulation environment which has both flexibility and efficiency. In this paper, a hardware software cosimulation environment is developed using the backplane approach and optimized synchronization. To seamlessly integrate a new simulator, this paper defines and implements the backplane protocol for communication and synchronization between client simulators. Automatic interface generation facility is also devised for more effective cosimulation environment. To enhance the performance of cosimulation backplane, a series of optimized hardware software synchronization methods are introduced. Efforts are focused on reducing control packets between simulators as well as concurrent execution of simulators without roll-back. The environment is implemented based on Ptolemy and validated with a QAM example run on different configurations. With optimized synchronization method, we have achieved about 7 times speed-up compared with the lock-step synchronization.

A decision-directed carrier phase recovery scheme for high-speed satellite communications is proposed. Since the estimation is performed in complex domain from the baseband signal, the scheme has fast acquisition performance, unlike the conventional PLL. This merit makes it applicable for various wireless systems such as wireless local area networks (LANs), wireless asynchronous transfer modes (ATMs) and local multipoint distribution systems (LMDSs) that need high-speed burst signal communications. Also, this scheme can be implemented easily because low pass filters (LPFs) are utilized in filtering the estimates in order to suppress the noise within the carrier recovery loop. Moreover it does not require any divider or voltage-controlled oscillator (VCO). The performance is analyzed through analytical methods and simulation.

This paper studies the application of a media synchronization mechanism to the interleaved transmission of video and audio specified by the H.223 Annex in PHS. The media synchronization problem due to network delay jitters in the interleaved transmission has not been discussed in either the Annex or any related standards. The slide control scheme, which has been proposed by the authors, is applied to live media. We also propose a QOS control scheme to control both quality of the media synchronization and that of the transmission delay. Through simulation we confirm the effectiveness of the slide control scheme and the QOS control scheme in the interleaved transmission.

A zerotree image-coding scheme is introduced that effectively exploits the inter-scale self-similarities found in the octave decomposition by a wavelet transform. A zerotree is useful for efficiently coding wavelet coefficients; its efficiency was proved by Shapiro's EZW. In the EZW coder, wavelet coefficients are symbolized, then entropy-coded for further compression. In this paper, we analyze the symbols produced by the EZW coder and discuss the entropy for a symbol. We modify the procedure used for symbol-stream generation to produce lower entropy. First, we modify the fixed relation between a parent and children used in the EZW coder to raise the probability that a significant parent has significant children. The modified relation is flexibly modified again based on the observation that a significant coefficient is more likely to have significant coefficients in its neighborhood. The three relations are compared in terms of the number of symbols they produce.

A novel zero-voltage-switched half-bridge converter is proposed. This converter achieves the zero-voltage switching while maintaining a constant frequency PWM control. Then the power conversion of high efficiency and low noise is realized at a higher switching frequency. In the experiment, a high efficiency of 83% is achieved for a low output voltage of 3.3 V, an output current of 30 A, and an input-voltage range of 200 to 400 V at the switching frequency of 400 kHz.

In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.

Reducing communication overhead is a key goal of program optimization for current scalable multiprocessors. A well-known approach to achieving this is to map tasks (indivisible units of computation) to processors so that communication and computation overlap as much as possible. In an earlier work, we developed a look-ahead scheduling heuristic for efficiently reducing communication overhead with the aim of decreasing the completion time of a given parallel program. In this paper, we report on an extension of the algorithm, which fills in the idle time slots created by interprocessor communication without increasing the algorithm's time complexity. The results of experiments emphasize the importance of optimally filling idle time slots in processors.

A 14. 4-in. diagonal EL display with 640128 pixels has been developed in red/green multicolor structures by using a new phosphor layer consisting of Zn1-xMgxS:Mn and ZnS:Mn. The display is designed for 240 Hz-frame rate, enabling the luminance to be improved by a factor of two. In addition, the contrast ratio is strongly enhanced by optimizing the black background structure and color filters. Improved characteristics make it possible for the EL panel to meet the requirements for the public information display taking advantages of high-reliability, crisp image and wide-viewing angle. Furthermore, the possibility of full-color EL displays will be described on the basis of "color by white" approach.

We discuss optimal rotation estimation from two sets of 3-D points in the presence of anisotropic and inhomogeneous noise. We first present a theoretical accuracy bound and then give a method that attains that bound, which can be viewed as describing the reliability of the solution. We also show that an efficient computational scheme can be obtained by using quaternions and applying renormalization. Using real stereo images for 3-D reconstruction, we demonstrate that our method is superior to the least-squares method and confirm the theoretical predictions of our theory by applying bootstrap procedure.

Due to a rather low phoneme recognition rate for noisy telephone speech, there may arise large differences between N-gram built upon recognized phoneme labels and those built upon original attached phoneme labels, which in turn would affect the performances of N-gram based language identification methods. Use of N-gram built upon recognized phoneme labels from the training data was evaluated and was shown to be more effective for the language identification. The performance of mixed phoneme recognizer, in which both language-dependent and language-independent phonemes were included, was also evaluated. Results showed that the performance was better than that using parallel language-dependent phoneme recognizers in which bias existed due to different numbers of phonemes among languages.

Initial leveling of strapdown inertial navigation system is a prerequisite work for distinguishing between gravity and acceleration effects in the accelerometer sensing's. This study presents an on-line methodology to resolve the initial leveling problem of a vehicle, which is subject to a large, long duration, and abrupt disturbance input with a deterministic nature under noisy circumstances. The developed method herein is the Kalman filter based scheme with a robust input estimator, generalized M estimator, and a testing criterion. The generalized M estimator identifies the unexpected disturbance inputs in real time. In addition, hypothetical testing based on the least-squares estimator is devised to detect the input's onset and presence. A required regression equation between the observed value of the residual sequence with an unknown input and theoretical residual sequence of the Kalman filter with no input is formulated. Input estimation and detection are then provided on the basis of the derived regression equation. Moreover, Monte Carlo simulations are performed to assess the superior capabilities of the proposed method in term of rapid responses, accuracy, and robustness. The efficient initial leveling can facilitate the entire alignment of the inertial system.

This letter proposes a new retransmission control scheme for slow-frequency-hopped communication systems, in which the number of (re)transmitted packets is adaptively decreased in a certain period. Performance of the proposed scheme is analyzed and compared with that of the conventional scheme in terms of the normalized throughput and the 98% packet transmission delay. The numerical results show the superiority of the proposed scheme.