Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.

High-speed collision detection is important to realize a highly-safe intelligent vehicle. In collision detection, high-computational power is required to perform matching operation between discrete points on surfaces of a vehicle and obstacles in real-world environment. To achieve the highest performance, a hierarchical matching scheme is proposed based on two representations: the coarse representation and the fine representation. A vehicle is represented as a set of rectangular solids in the fine representation (fine rectangular solids), and the coarse representation, which is also a set of rectangular solids, is produced by enlarging the fine representation. If collision occurs between an obstacle discrete point and a rectangular solid in the coarse representation (coarse rectangular solid), then it is sufficient to check the only fine rectangular solids contained in the coarse one. Consequently, checks for the other fine rectangular solids can be omitted. To perform the hierarchical matching operation in parallel, a hierarchically-content-addressable memory (HCAM) is proposed. Since there is no need to perform matching operation in parallel with fine rectangular solids contained in different coarse ones, the fine ones are mapped onto a matching unit. As a result, the number of matching units can be reduced without decreasing the performance. Under the condition of the same execution time, the area of the HCAM is reduced to 46.4% in comparison with that of the conventional CAM in which the hierarchical matching scheme is not used.

This paper analyzes the operations of a CMOS multivibrator-based chaos generator. The equations representing the shape of the first return map are formulated and confirmed by comparison with experimental results, and the design principles are obtained.

This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as (log2ppv + p(n-v) + 1) pn-1 to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.

In this paper, we present the theoretical development to stabilize a class of uncertain time-delay system. The system under consideration is described in state space model containing distributed delay, uncertain parameters and disturbance. The main idea is to transform the system state into an equivalent one, which is easier to analyze its behavior and stability. Then, a computational method of robust controller design is presented in two parts. The first part is based on solving a Riccati equation arising in the optimal control theory. In the second part, the finite dimensional Lyapunov min-max approach is employed to cope with the uncertainties. Finally, we show how the resulting control law ensures asymptotic stability of the overall system.

This paper presents two competitive learning methods with the objective of avoiding the initial dependency of weight (reference) vectors. The first is termed the refractory and competitive learning algorithm. The algorithm has a refractory period: Once the cell has fired, a winner unit corresponding to the cell is not selected until a certain amount of time has passed. Thus, a specific unit does not become a winner in the early stage of processing. The second is termed the creative and competitive learning algorithm. The algorithm is presented as follows: First, only one output unit is prepared at the initial stage, and a weight vector according to the unit is updated under the competitive learning. Next, output units are created sequentially to a prespecified number based on the criterion of the partition error, and competitive learning is carried out until the ternimation condition is satisfied. Finally, we discuss algorithms which have little dependence on the initial values and compare them with the proposed algorithms. Experimental results are presented in order to show that the proposed methods are effective in the case of average distortion.

It is an important problem in signal processing, system realization and system identification to find linear discrete-time systems which are consistent with given covariance parameters. This problem is formulated as a problem of finding discrete-time positive real functions which interpolate given covariance parameters. Various investigations have yielded several significant solutions to the problem, while there remains an important open problem concerning the McMillan degree. In this paper, we use more general input-output characteristics than covariance parameters and consider finding discrete-time positive real matrix functions which interpolate such characteristics. The input-output characteristics are given by the coefficients of the Taylor series at some complex points in the open unit disk. Thus our problem is a generalization of the interpolation problem of covariance parameters. We reduce the problem to a directional interpolation problem with a constraint and develop the solution by a state-space based new approach. The main results consist of the necessary and sufficient condition for the existence of the discrete-time positive real matrix function which interpolates the given characteristics and has a limited McMillan degree, and a parameterization of all such functions. These are a contribution to the open problem and a generalization of the previous result.

In this paper, we propose a new structure of blind equalizer and its cost function. The proposed cost function is a quadratic form and has the unique solution. In addition, the proposed scheme can employ iterative algorithms which achieve less computational complexity and can be easily realized in real time processing. In order to verify the effectiveness of the proposed schemes, several computer simulations including a 64-QAM signal equalization have been shown.

A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)130 mm (D) 10 mm (H). Using the receiver module, a fast acquisition time of 9 bits and receiver sensitivity penalty of less than 1.5 dB due to re-synchronization were measured.

We have developed an InP-based monolithic optical frequency discriminator consisting of a temperature-insensitive optical filter and dual photodiodes. This integrated device detects the optical frequency deviation of the input light as differential photocurrent from the dual photodiodes, and the photocurrent is fedback to the light source for frequency stabilization through a differential amplifier. The FSR and extinction ratio of the filter are 50 GHz and 20 dB. The total opto-electronic conversion efficiency is 40%. In a frequency stabilization experiment using the developed discriminator, the frequency fluctuation of a DFB laser was reduced to less than 10 MHz.

In this letter, the novel mapping network named self-organizing relationship (SOR) network, which can approximate the desired I/O relationship by employing the modified Kohonen's learning law, is proposed. In the modified Kohonen's learning law, the weight vectors are updated to be attracted to or repulsed from the input vector.

A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)130 mm (D) 10 mm (H). Using the receiver module, a fast acquisition time of 9 bits and receiver sensitivity penalty of less than 1.5 dB due to re-synchronization were measured.

We have developed a low-latency, error-correcting-code-(ECC-)adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections. A new frame-coding technique called shuffled mB1C encoding, which requires no clock-rate conversion circuit and no data buffering, and a new skew-measurement method which is suitable for ECC adaptation have been developed for the compensation. Full-digital skew-compensation circuits using these new techniques were able to compensate for a two-clock-cycle skew, even when one transmission channel was removed. The maximum latency for skew compensation was only five clock cycles.

A 1.55-µm hybrid integrated wavelength-converter module was fabricated using a two-channel spot-size converter integrated semiconductor optical amplifier (SS-SOA) on a planar-lightwave-circuit (PLC) platform. Clear eye opening and penalty-free wavelength conversion were obtained at 2.5-Gb/s modulation with a wide wavelength difference of 46 nm. The module showed good characteristics including low insertion loss (0.1 dB), and high conversion efficiency (-0.2 dB). It also showed stable wavelength conversion for as wide as a 13 temperature range.

Coaxial-core erbium-doped fiber amplifiers (EDFA's) having a property of self-regulated gain spectrum are developed. The operation of a coaxial-core EDFA is based on the partial separation of the light paths for different wavelength channels in the directionally-coupled waveguides of a coaxial-core geometry. The degree of channel equalization depends on the geometrical and optical parameters of the coaxial-core EDFA and on relative channel power levels. A numerical analysis based on the coupled-mode theory and on the rate equation shows that, under fully optimized conditions, a coaxial-core EDFA provides equalization rates in excess of -0.4 dB per dB of input-power imbalance in the case with two WDM channels. A cascade experiment demonstrates the effect of coaxial-core EDFA's toward channel-power equalization in fiber links with a small number of WDM channels.

We have developed a low-latency, error-correcting-code-(ECC-)adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections. A new frame-coding technique called shuffled mB1C encoding, which requires no clock-rate conversion circuit and no data buffering, and a new skew-measurement method which is suitable for ECC adaptation have been developed for the compensation. Full-digital skew-compensation circuits using these new techniques were able to compensate for a two-clock-cycle skew, even when one transmission channel was removed. The maximum latency for skew compensation was only five clock cycles.

A 1.55-µm hybrid integrated wavelength-converter module was fabricated using a two-channel spot-size converter integrated semiconductor optical amplifier (SS-SOA) on a planar-lightwave-circuit (PLC) platform. Clear eye opening and penalty-free wavelength conversion were obtained at 2.5-Gb/s modulation with a wide wavelength difference of 46 nm. The module showed good characteristics including low insertion loss (0.1 dB), and high conversion efficiency (-0.2 dB). It also showed stable wavelength conversion for as wide as a 13 temperature range.

Coaxial-core erbium-doped fiber amplifiers (EDFA's) having a property of self-regulated gain spectrum are developed. The operation of a coaxial-core EDFA is based on the partial separation of the light paths for different wavelength channels in the directionally-coupled waveguides of a coaxial-core geometry. The degree of channel equalization depends on the geometrical and optical parameters of the coaxial-core EDFA and on relative channel power levels. A numerical analysis based on the coupled-mode theory and on the rate equation shows that, under fully optimized conditions, a coaxial-core EDFA provides equalization rates in excess of -0.4 dB per dB of input-power imbalance in the case with two WDM channels. A cascade experiment demonstrates the effect of coaxial-core EDFA's toward channel-power equalization in fiber links with a small number of WDM channels.

We have developed an InP-based monolithic optical frequency discriminator consisting of a temperature-insensitive optical filter and dual photodiodes. This integrated device detects the optical frequency deviation of the input light as differential photocurrent from the dual photodiodes, and the photocurrent is fedback to the light source for frequency stabilization through a differential amplifier. The FSR and extinction ratio of the filter are 50 GHz and 20 dB. The total opto-electronic conversion efficiency is 40%. In a frequency stabilization experiment using the developed discriminator, the frequency fluctuation of a DFB laser was reduced to less than 10 MHz.

Steady-state characteristics of the push-pull inverter with a piezoelectric transformer are analyzed. The piezoelectric transformer operating in the 3rd-order longitudinal vibration mode is used in place of a conventional magnetic transformer to produce a high output voltage to light up a cold cathode fluorescent lamp. The circuit operation, the load characteristics, the efficiency and the ZVS conditions are analyzed using equivalent circuits. These analytical results are confirmed by experiments. An example of the output current control is also shown.