The evolution of Multiple-Valued Logic (MVL) circuits has been inexorably tied to the rapid technological changes induced by evolving needs and emerging developments in computing methodologies. Unfortunately for MVL, the numbers of designers of technologies and circuits whose lives are dedicated to the improvement of binary techniques, are large and overwhelming. Correspondingly, technological developments in MVL typically await the appearance of a problem or technique in the larger binary world to motivate and/or make possible some new advance. Such opportunities are inevitably quite transient since each such problem is simultaneously attacked by many others of a more conventional bent, and, as well, each technological change begets yet another, quickly. It is in the sensing of this reality that the present paper is written. Correspondingly, its thrust is two-fold: One target is the possibility of encouraging a leap ahead through modest technological projection. The other is the possibility of identifying application areas that already exist in this unbalanced competition, but which are specially suited to multiple-valued solutions. For example, it has been clear for decades that one such area is that of arithmetic. Correspondingly, we in MVL must strive quickly to concentrate our efforts on applications that exploit such demonstrable strengths. Some such applications are includes here; others are visible historically, many probably remain to be found: Search on!

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

A further study on a VLSI system compiler, named VEGA (VLSI Embodiment for General Algorithms), is presented. It maps a general digital signal processing algorithm onto a neo-systolic array, which is a VLSI oriented multiprocessor array. Highly complicated mapping problem is divided into subproblems such as modularization, operation grouping, processor placement, scheduling, control logic synthesis, and mask pattern generation. In this paper, the modularization technique is proposed which homogenizes all the operations of the processing algorithm to multiply-add operations. The processor placement algorithm to map processing algorithm onto a neo-systolic array so as to minimize data transfer time is also proposed.

Research in optical microwave interaction, at its earlier stages, was spured by the desire to make an optically fed and controlled phased array antenna with monolithic microwave integrated circuit (MMIC) transmit/receive (T/R) modules. In the first part of this paper experimental results are presented demonstrating an optically fed phased array antenna operating at C-band in the 5.5 to 5.8 GHz frequency range. The present system consists of two optically fed 14 subarrays with MMIC based active T/R modules. Custom designed fiber optic links have been employed to provide distribution of data and frequency reference signals to phased array antenna. One of the challenges of the future is the development of better interfaces between electronic (microwave) and optical components, including the chip level merging of photonic and electronic components on III-V compounds. This aspect of the research is covered in the second half of the paper.

This paper reviews the application of optical technologies to phased array antennas. The performance of the fibre transmission medium and of sources and detectors is reviewed, leading to simple expressions for transmission loss and noise performance. Both coherent and non-coherent beam forming techniques are considered. Future trends, including the use of optical amplifiers and coherent signal generation, will also be discussed.

A typical fault-tolerance technique of systolic arrays is to include redundant processors and links so that the array is reconfigurable when some processors fail. Another typical technique is to implement each processor by a majority voter and N (N3) copies of processors so that the faults of up to N-2 copies of processors can be masked without reconfiguration. This paper proposes a systolic linear array called reconfigurable modular redundant linear array (RMA) that combines these techniques with N4. When up to 2 copies of each processor fail in RMA, the faults can be masked without reconfiguration. When some voters or more than 2 copies of a processor fail, RMA can be reconfigured by specifying a new switch pattern. In order to perform reconfiguration efficiently, we present a reconfiguration algorithm with time complexity O (n), where n is the number of processors in RMA.

A high resolution iterative algorithm for estimating the direction-of-arrival of multiple wide band sources is proposed in this paper. For equally spaced array structure, two Unitary Transform based approaches are proposed in frequency domain for signal subspace processing in both coherent multipath and incoherent environment. Given a priori knowledge of the initial estimates of DOA, with proper spatial prefiltering to separate multiple groups of closely spaced sources, our proposed algorithm is shown to have high resolution capability even in coherent multipath environment without reducing the angular resolution, compared with the use of subarray. Compared with the conventional algorithm, the performance by the proposed algorithm is shown by the simulations to be improved under low Signal to Noise Ratio (SNR) while the performance is not degraded under high SNR. Moreover the computation burden involved in the eigencomputation is largely reduced by introducing the Pesudo-Hermitian matrix approximation.

A detailed numerical solution of the design criteria of in-phase lateral and single-longitudinal-mode operation GaInAsP/InP DFB laser arrays is presented. The analysis, including broad-area pumped and stripe-geometry pumped index-guided arrays, was carried out on the basis of the eigenvalue equation method. It is shown that there exists a cut-off array pitch co, at which all of the higher-order array modes are cut off. For the pitch larger than the cut-off pitch co, the modal discrimination is evaluated by the threshold gain difference between the in-phase lateral and higher-order array modes. As a result, the modal discrimination was found to decrease with the increase of the number of elements and the array pitch which is limited to be smaller than twice the cut-off pitch co to attain a stable in-phase lateral- and single-longitudinal-mode operation.

Frequency Selective Screens (FSS) with conductor or complementary aperture array are investigated. The electric current distribution on conductor or the magnetic current distribution on aperture is determined by the moment method in the spectral domain. In addition, the power reflection coefficients are calculated and the scattering properties are considered.

This paper proposes a method to estimate the waveform of a specified sound source in a noisy and reverberant environment using a sensor array. Previously, we proposed an iterative method to estimate the waveform. However, in this method the effect of reflection sound reduces to 1/M, where M is the number of microphones. Therefore, to solve the reverberation problem, we propose a new method using inverse filters of the transfer functions from the sound sources to each microphone. First, the transfer function from each sound source to each microphone is measured by the cross-spectrum technique and each inverse filter is calculated by the QR method. Then the initially estimated waveform of a sound source is the averaged signal of the inverse filter outputs. Since this waveform still contains the effects of the other sound sources, the iterative technique is adopted to estimate the waveform more precisely, reducing the effects of the other sound and the reflection sound. Some computer simulations and experiments were carried out. The results show the effectiveness of our method.

A new design method is proposed for realizing a hypercube network (HC) structured multicomputer system on a wafer using wafer-scale integration (WSI). The probability that an HC can be constructed on a wafer is higher in this method than in the conventional method; this probavility is called a construction probability. We adopt the FUSS method for the processor (PE) address allocation in our desing because it has a high success probability in the allocation. Even if the design renders the address allocation success probalility hegher, it is of no use if it makes either the maximum wiring length between PEs or the array size (wiring area) larger. A new wiring channel structure capable of connecting PEs on a wafer is proposed in this paper, where a channel, called a basic channel, is used. A one-dimensional-array sub-HC row network (RN) or column networks (CN) can be constructed using the basic channel. The sub-HC construction method, which embeds wirings into the basic channel, is also proposed. It requires almost the same wiring width as conventional method. However, it has an advantage in that maximum wiring length between PEs can be about half that of the conventional method. If PEs must be shifted in the case of PE defects, they can be shifted and connected to the basic channel using other PE shifting channels, and an RN or CN can be constructed. The maximum wiring length between PEs, array size, and construction probability will also be derived, and it will be shown that the proposed design is superior to the conventional one.

This paper describes a novel Recessed Stacked Capacitor (RSTC) structure for 256 Mbit DRAMs, which can realize the requirements for both fine-pattern delineation with limited depth of focus and high cell capacitance. New technologies involved are the RSTC process, 0.25 µm phase-shift lithography and CVD-tungsten plate technology. An experimental memory array has been fabricated with the above technologies and 25 fF/cell capacitance is obtained for the first time in a 0.61.2 µm2 (0.72 µm2) cell.

An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

This paper describes a VLSI processor architecture designed for a back-propagation accelerator. Three techniques are used to accelerate the simulation. The first is a multi-processor approach where a neural network simulation is suitable for parallel processing. By constructing a ring network using several processors, the simulation speed is multiplied by the number of the processors. The second technique is internal parallel processing. Each processor contains 4 multipliers and 4 ALUs that all work in parallel. The third technique is pipelining. The connections of eight functional units change according to the current stage of the back-propagation algorithm. Intermediate data is sent from one functional unit to another without being stored in extra registers and data is processed in a pipeline manner. The data is in 24-bit floating point format (18-bit mantissa and 6-bit oxponent). The chip has about 88,000 gates, including microcode ROM for processor control, the processor is designed using 0.8-µm CMOS gate arrays, and the estimated performance at 40 MHz is 20 million connection updates per second (MCUPS). For a ring network with 4 processors, performance can be enhanced up to 90 MCUPS.

The paper describes the design considerations, fabrication process and performance of the newly developed 1-K ECL gate array implemented with fully self-aligned AlGaAs/GaAs hoterojunction bipolar transistors (HBTs). This gate array consists of 960 three-input OR/NOR ECL basic gates. It contains about 7,600 transistors in a chip area 8.15-mm8.45-mm. The basic (FI=FO=1, wiring length L=0-mm) and loaded (FI=FO=3, L=1-mm) gates exhibit delay times of 33-ps and 82-ps, respectively, with 8.5-mW/gate power dissipation. From the measured values, fan-in, fan-out and wiring delay times of 9-ps/FI, 7-ps/FO and 17-ps/mm are estimated, respectively. These results are in good agreement with the designed results obtained using "SPICE" simulation.

An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.

This paper addresses fault tolerance of a processor array that is reconfigurable by replacing faulty processors with spare processors. The fault tolerance of such a reconfigurable array depends on not only an algorithm for spare processor assignment but also the folloving factor of an organization of spare processors in the reconfigurable array: the number of spare processors; the number of processors that can be replaced by each spare processor; and how spare processors are connected with processors. We discuss a relationship between fault tolerance of reconfigurable arrays and their organizations of spare processors in terms of the smallest size of fatal sets and the reliability function. The smallest size of fatal sets is the smallest number of faulty processors for which the reconfigurable array cannot be failure-free as a processor array system no matter what reconfiguration is used. The reliability function is a function of time t whose value is the probability that the reconfigurable array is failure-free as a processor array system by time t when the best possible reconfiguration is used. First, we show that the larger smallest size of fatal sets a reconfigurable array has, the larger reliability function it has by some time. It suggests that it is important to maximize the smallest size of fatal sets in orer to improve the reliability function as well. Second, we present the best possible smallest size of fatal sets for nn reconfigurable arrays using 2n spare processor each of which is connected with n processors. Third, we show that the nn reconfigurable array previously presented in a literature achieves the best smallest size of fatal sets. That is, it is optimum with respect to the smallest size of fatal sets. Fourth, we present an uppr bound of the reliability function of the optimum nn reconfigurable array using 2n spare processors.

In this paper we review the recent progress and basic technology of vertical cavity surface emitting lasers together with related parallel surface operating optical devices. First, the concept of surface emitting lasers is presented, and then currently developed device technologies will be reviewed. We will feature several technical issues, such as multi-layer structures, 2-dimensional arrays, photonic integration, etc. Lastly, future prospects for parallel lightwave systems will be discussed.

In this paper we review the recent progress and basic technology of vertical cavity surface emitting lasers together with related parallel surface operating optical devices. First, the concept of surface emitting lasers is presented, and then currently developed device technologies will be reviewed. We will feature several technical issues, such as multi-layer structures, 2-dimensional arrays, photonic integration, etc. Lastly, future prospects for parallel lightwave systems will be discussed.