Omni-directional images have been used in wide range of applications including virtual/augmented realities, self-driving cars, robotics simulators, and surveillance systems. For these applications, it would be useful to estimate saliency maps representing probability distributions of gazing points with a head-mounted display, to detect important regions in the omni-directional images. This paper proposes a novel saliency-map estimation model for the omni-directional images by extracting overlapping 2-dimensional (2D) plane images from omni-directional images at various directions and angles of view. While 2D saliency maps tend to have high probability at the center of images (center bias), the high-probability region appears at horizontal directions in omni-directional saliency maps when a head-mounted display is used (equator bias). Therefore, the 2D saliency model with a center-bias layer was fine-tuned with an omni-directional dataset by replacing the center-bias layer to an equator-bias layer conditioned on the elevation angle for the extraction of the 2D plane image. The limited availability of omni-directional images in saliency datasets can be compensated by using the well-established 2D saliency model pretrained by a large number of training images with the ground truth of 2D saliency maps. In addition, this paper proposes a multi-scale estimation method by extracting 2D images in multiple angles of view to detect objects of various sizes with variable receptive fields. The saliency maps estimated from the multiple angles of view were integrated by using pixel-wise attention weights calculated in an integration layer for weighting the optimal scale to each object. The proposed method was evaluated using a publicly available dataset with evaluation metrics for omni-directional saliency maps. It was confirmed that the accuracy of the saliency maps was improved by the proposed method.

Physical Unclonable Function (PUF) is a promising lightweight hardware security primitive that can extract device fingerprints for encryption or authentication. However, extracting fingerprints from either the chip or the board individually has security flaws and cannot provide hardware system-level security. This paper proposes a new Chip-PCB hybrid PUF(CPR PUF) in which Weak PUF on PCB is combined with Strong PUF inside the chip to generate massive responses under the control of challenges of on-chip Strong PUF. This structure tightly couples the chip and PCB into an inseparable and unclonable unit thus can verify the authenticity of chip as well as the board. To improve the uniformity and reliability of Chip-PCB hybrid PUF, we propose a lightweight key generator based on a reliability self-test and debiasing algorithm to extract massive stable and secure keys from unreliable and biased PUF responses, which eliminates expensive error correction processes. The FPGA-based test results show that the PUF responses after robust extraction and debiasing achieve high uniqueness, reliability, uniformity and anti-counterfeiting features. Moreover, the key generator greatly reduces the execution cost and the bit error rate of the keys is less than 10-9, the overall security of the key is also improved by eliminating the entropy leakage of helper data.

This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.

This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). This paper proposes an approximation-based implementation method for an MEP tracking system over a wide voltage region. This paper focuses on the MEP characteristics that the energy loss is sufficiently small even though the voltage point changes near the MEP. For example, the energy loss is less than 5% even though the estimated MEP differs by a few tens of millivolts in comparison with the actual MEP. Therefore, the complexity for determining the MEP is relaxed by approximating complex operations such as the logarithmic or the exponential functions in the MEP tracking algorithm, which leads to hardware-/software-efficient implementation. When the MEP tracking algorithm is implemented in software, the MEP estimation time is reduced from 1ms to 13µs by the proposed approximation. When implemented in hardware, the proposed method can reduce the area of an MEP estimation circuit to a quarter. Measurement results of a 32-bit RISC-V processor fabricated in a 65-nm SOTB process technology show that the energy loss introduced by the proposed approximation is less than 2% in comparison with the MEP operation. Furthermore, we show that the MEP can be tracked within about 45 microseconds by the proposed MEP tracking system.

This paper deals with a state-space approach for adaptive second-order IIR notch digital filters with constrained poles and zeros. A simplified iterative algorithm is derived from the gradient-descent method to minimize the mean-squared output of an adaptive notch digital filter. Then, stability and parameter-estimation bias are analyzed for the simplified iterative algorithm. A numerical example is presented to demonstrate the validity and effectiveness of the proposed adaptive state-space notch digital filter and parameter-estimation bias analysis.

Hansen, Kaplan, Zamir and Zwick (STOC 2019) introduced a systematic way to use “bias” for predicting an assignment to a Boolean variable in the process of PPSZ and showed that their biased PPSZ algorithm achieves a relatively large success probability improvement of PPSZ for Unique 3SAT. We propose an additional way to use “bias” and show by numerical analysis that the improvement gets increased further.

In the upcoming Internet of Things era, reducing energy consumption of embedded processors is highly desired. Minimum Energy Point Tracking (MEPT) is one of the most efficient methods to reduce both dynamic and static energy consumption of a processor. Previous works proposed a variety of MEPT methods over the past years. However, none of them incorporate their algorithms with practical real-time operating systems, although edge computing applications often require low energy task execution with guaranteeing real-time properties. The difficulty comes from the time complexity for identifying an MEP and changing voltages, which often prevents real-time task scheduling. The conventional Dynamic Voltage and Frequency Scaling (DVFS) only scales the supply voltage. On the other hand, MEPT needs to adjust the body bias voltage in addition. This additional tuning knob makes MEPT much more complicated. This paper proposes an approximate MEPT algorithm, which reduces the complexity of identifying an MEP down to that of DVFS. The key idea is to linearly approximate the relationship between the processor frequency, supply voltage, and body bias voltage. Thanks to the approximation, optimal voltages for a specified clock frequency can be derived immediately. We also propose a task scheduling algorithm, which adjusts processor performance to the workload and then provides a soft real-time capability to the system. The operating system stochastically adjusts the average response time of the processor to be equal to a specified deadline. MEPT will be performed as a general task, and its overhead is considered in the calculation of the frequency. The experiments using a fabricated test chip and on-chip sensors show that the proposed algorithm is a maximum of 16 times more energy-efficient than DVFS. Also, the energy loss induced by the approximation is only 3% at most, and the algorithm does not sacrifice the fundamental real-time properties.

A method for runtime energy optimization based on the supply voltage (Vdd) and the threshold voltage (Vth) scaling is proposed. This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). The MEP dynamically fluctuates depending on the operating conditions determined by a target delay constraint, an activity factor and a chip temperature. In order to track the MEP, this paper proposes a closed-form continuous function that determines the MEP over a wide operating performance region ranging from the above-threshold region down to the sub-threshold region. Based on the MEP determination formula, an MEP tracking algorithm is also proposed. The MEP tracking algorithm estimates the MEP even though the operating conditions widely change. Measurement results based on a 32-bit RISC processor fabricated in a 65-nm Silicon On Thin Buried oxide (SOTB) process technology show that the proposed method estimates the MEP within a 5% energy loss in comparison with the actual MEP operation.

This paper investigates an adaptive notch digital filter that employs normal state-space realization of a single-frequency second-order IIR notch digital filter. An adaptive algorithm is developed to minimize the mean-squared output error of the filter iteratively. This algorithm is based on a simplified form of the gradient-decent method. Stability and frequency estimation bias are analyzed for the adaptive iterative algorithm. Finally, a numerical example is presented to demonstrate the validity and effectiveness of the proposed adaptive notch digital filter and the frequency-estimation bias analyzed for the adaptive iterative algorithm.

This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.

This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0dB.

We show that imperfection in an IQ-modulator degrades the accuracy of the auto bias control (ABC) circuit connected to the modulator's complementary port. Theoretical analyses show that the IQ-modulator constructed by a nested Mach-Zehnder modulator with a low extinction ratio can distort a constellation of modulated light observed at the complementary port. We propose an auto calibration technique for the ABC circuit that can effectively suppress this degradation. Experimental results using 32-Gbaud, 16-QAM signals showed the measured Q-factor improved by 0.5dB with our proposed technique.

With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and Vth temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.

This paper proposes a technique that increases the lifetime of large scale integration (LSI) devices. As semiconductor technology improves at miniaturizing transistors, aging effects due to bias temperature instability (BTI) seriously affects their lifetime. BTI increases the threshold voltage of transistors thereby also increasing the delay of an electronics device, resulting in failures due to timing violations. To compensate for aging-induced timing violations, we exploit configurable approximate computing. Assuming that target circuits have exact and approximate modes, they are configured for the approximate mode if an aging sensor predicts violations. Experiments using an example circuit revealed an increase in its lifetime to >10 years.

This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.

Differential code biases (DCBs) are important parameters that must be estimated accurately for precise positioning and Satellite Based Augmentation Systems (SBAS) ionospheric related parameter generation. In this paper, in order to solve the performance degradation problem of the traditional minimum STD searching algorithm in disturbed ionosphere status and in geomagnetic low latitudes, we propose a linear planar based minimum STD searching algorithm. Firstly, we demonstrate the linear planar trend of the local vertical TEC and introduce the linear planar model based minimum standard variance searching method. Secondly, we validate the correctness of our proposed method through theoretical analysis and propose bias detection to avoid large estimation bias. At last, we show the performance of our proposed method under different geomagnetic latitudes, different seasons and different ionosphere status. The experimental results show that for the traditional minimum STD searching algorithm based on constant model, latitude difference is the key factor affecting the performance of DCB estimation. The DCB estimation performance in geomagnetic mid latitudes is the best, followed by the high latitudes and the worst is for the low latitudes. While the algorithm proposed in this paper can effectively solve the performance degradation problem of DCB estimation in geomagnetic low latitudes by using the linear planar model which is with a higher degree of freedom to model the local ionosphere characteristics and design dJ to screen the epochs. Through the analysis of the DCB estimation results of a large number of stations, it can be found that the probability of large estimation deviation of the traditional method will increase obviously under the disturb ionosphere conditions, but the algorithm we proposed can effectively control the amplitude of the maximum deviation and alleviate the probability of large estimation deviation in disturb ionosphere status.

The estimation of the matrix rank of harmonic components of a music spectrogram provides some useful information, e.g., the determination of the number of basis vectors of the matrix-factorization-based algorithms, which is required for the automatic music transcription or in post-processing. In this work, we develop an algorithm based on Stein's unbiased risk estimator (SURE) algorithm with the matrix factorization model. The noise variance required for the SURE algorithm is estimated by suppressing the harmonic component via median filtering. An evaluation performed using the MIDI-aligned piano sounds (MAPS) database revealed an average estimation error of -0.26 (standard deviation: 4.4) for the proposed algorithm.

Body bias generators are useful circuits that can reduce variability and power dissipation in LSI circuits. However, the amplifier implemented into the body bias generator is difficult to design because of its complexity. To overcome the difficulty, this paper proposes a clearer cell-based design method of the amplifier than the existing cell-based design methods. The proposed method is based on a simple analytical model, which enables to easily design the amplifiers under various operating conditions. First, we introduce a small signal equivalent circuit of two-stage amplifiers by which we approximate a three-stage amplifier, and introduce a method for determining its design parameters based on the analytical model. Second, we propose a method of tuning parameters such as cell-based phase compensation elements and drive-strength of the output stage. Finally, based on the test chip measurement, we show the advantage of the body bias generator we designed in a cell-based flow over existing designs.

The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (VG=VD). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.

A novel time-series relationship among four consecutive real-valued single-tone sinusoid samples is proposed based on their linear prediction property. In order to achieve unbiased frequency estimates for a real sinusoid in white noise, based on the proposed four-point time-series relationship, a constrained least squares cost function is minimized based on the unit-norm principle. Closed-form expressions for the variance and the asymptotic expression for the variance of the proposed frequency estimator are derived, facilitating a theoretical performance comparison with the existing three-point counterpart, called as the reformed Pisarenko harmonic decomposer (RPHD). The region of performance advantage of the proposed four-point based constrained least squares frequency estimator over the RPHD is also discussed. Computer simulations are conducted to support our theoretical development and to compare the proposed estimator performance with the RPHD as well as the Cramer-Rao lower bound (CRLB).