A multihop connection scheme, where one or more mobile terminals relay transmission signals using the same access scheme between an end user terminal and its destination base station, is a promising approach to overcome reduction in cell size caused by high bit-rate data transmission. In a general radio communication system, the coverage area and system throughput are closely interrelated. In this paper, the performance of a multihop cellular network employing a CDMA access scheme, which is a promising candidate for beyond the third generation, is studied in terms of the coverage area and system throughput by conducting a link level simulation. The results show that a multihop connection expands the coverage area, especially in the case of light traffic, and also has an advantage in system throughput.

Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase.

In order to achieve omni-directional coverages on base station antennas for fixed wireless access systems (FWA), a TM01 mode conical horn with 4.6λ aperture size was employed as a feed horn for an axisymmetrical reflector antenna. Here, a shaped dielectric lens was inserted in the conical horn so as to achieve low sidelobe radiation characteristics. However, it was pointed out that radiation pattern shaping ability was degraded in this small lens antenna. In this paper, deteriorations of aperture distributions in a shaped lens are clarified through FDTD calculations. Severe phase delays are shown in the aperture phase distributions. A novel lens shaping method of compensating the phase delays is developed. Aperture distributions and radiation patterns of the corrected lens are estimated through FDTD calculations. Satisfactory uniform phase distributions in aperture distributions and low sidelobe radiation patterns are ensured.

A scheme to evaluate the number of users and cell coverage of a WCDMA supporting multi-rate traffic is newly presented through calculation of the realizable Erlang capacity from a derived blocking probability and the path loss from the COST231 Walfisch-Ikegami (WI) model. Based on this analytical scheme, we evaluate the voice-data Erlang capacities at various data rates of 15 kbps to 480 kbps and the relationship between the cell coverage and the number of active users from them. When the value of Eb/Io is low from 4 dB to 3 dB under voice user capacity of 50 Erlang at 8 kbps, the result shows that the data user capacity is increased to 10 Erlang at low rate of 15 kbps and the cell coverage is enlarged to 100 m, and it is also shown that its capacity is increased to 0.2 Erlang at high rate of 480 kbps and its coverage to 50 m.

As we enter the deep submicron era, the costs to maintain the quality of shipped products increases significantly. Unfortunately, even 100% coverage of the widely used single stuck-at faults cannot guarantee that the defect level of the shipped chips is low enough. This is due to the fact that the stuck-at fault model does not cover all catastrophic defects. Moreover, it is difficult to estimate the difference between stuck-at fault coverage and defect coverage. Multiple fault models or test techniques are usually adopted in the test process, each having its corresponding fault coverage. However, the relationship between the defect level and those individual fault coverages remains to be explored. In this paper, we first propose the concept of multi-model fault coverage (MFC) instead of the fault coverage based on a single fault model. The multi-model fault coverage for nonequiprobable faults is presented, and the multi-model fault coverage for equiprobable faults is shown to be a special case of nonequiprobable faults. The relationship between defect level, fabrication yield, and multi-model fault coverage is then derived. We also analyze the defect level error between the predicted defect level and the physical defect level. An algorithm is also proposed for estimating the number of fault models required in order to achieve sufficient accuracy. Experimental results show that multi-model fault coverage can be used to predict the defect level more precisely. As the number of fault models increases, the defect level error reduces significantly. Our approach is efficient for product quality prediction, especially for deep sub-micron devices.

Software and its systems are more complicated than a decade ago, and the systems are used for mission critical business, flight control and so on which often require high assurance systems. In this circumstance, we often use black-box testing. The question now arises that black-box testing does not generate numerical value of testing result but empirical. Thus, in this research, we develop and enhance FSM (Finite State Machine) testing method which can produce code coverage rate as numerical value. Our developed FSM testing by code coverage focuses on not only software system behavior but also data. We found higher code coverage rate, which indicates quality of system, by this method than existing black box testing method.

This paper compares by computer simulation the achievable throughput performance employing fast packet scheduling algorithms focusing on the throughput of each user in High Speed Downlink Packet Access (HSDPA). Three packet scheduling algorithms are employed: the Maximum carrier-to-interference power ratio (CIR), Proportional Fairness (PF), and Round Robin (RR) methods. The simulation results elucidate that although the Maximum CIR method achieves an aggregated user throughput within a cell higher than that using the PF and RR methods, the PF method is advantageous because it enhances the user throughput for a large number of users with a lower received signal-to-interference power ratio (SIR), who are located outside the normalized distance of 0.6-0.7 from a cell site (this corresponds to the area probability of 50-60% within the cell) compared to the Maximum CIR method. It is also shown that when the PF method is employed, the probability of user throughput of greater than 2 Mbps in the vicinity of the cell site becomes approximately 45% (5%) for L = 1-path (2-path) fading channel, while it is almost 80% (50%) when using the Maximum CIR method. Finally, we show that the average user throughput in a 2-path Rayleigh fading channel is reduced by approximately 30% compared to that in a 1-path channel due to severe multipath interference (MPI) and that the average user throughput is strongly affected by the total traffic produced within a cell, which is directly dependent on the number of users within a cell and the data size per packet call.

We have specified typical fabrication defects of the current injection logic gates with four Josephson junctions (4JL gates), and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that current testing may possibly achieve a high defect coverage while logic testing cannot detect almost half defects.

For indoor wireless communication systems, transceivers need to be placed strategically to achieve optimum communication coverage area at the lowest cost. Unfortunately the coverage region for a transceiver depends heavily on the type of building and on the placement of walls within the building. This paper proposed a slab model to simulate the wave transmission in the wall and employed this simple path loss model to predict the coverage region. This method prevents the complicated computation of wave propagation, so it could predict the coverage area real time. Numerical results show predicted path loss date are well agreed with the measurement ones.

BaSnO3 is proposed as a new insulating material with good surface coverage of the lower superconductor electrode for superconductor/insulator/superconductor (SIS) tunnel junctions made of high-Tc superconductor YBa2Cu3Ox (YBCO). This paper reports on investigation of the epitaxial nature of BaSnO3 on YBCO thin films and YBCO/BaSnO3 /YBCO trilayer formation that are grown in situ by reactive co-evaporation in oxygen radicals. Investigation was done by reflection high-energy electron diffraction (RHEED), atomic force microscopy (AFM), and X-ray diffraction (XRD). these observations confirm that (001)-oriented YBCO and (100)-oriented BaSnO3 thin films with atomically smooth surfaces grow epitaxially on each other. In addition, cross-sectional transmission electron microscopy (TEM) observation reveals that an approximately 4-nm-thick layer of BaSnO3 perfectly covers the lower YBCO thin film surface steps to a height of 1 to 2 unit cells of YBCO. The zero-resistance critical temperature Tc zero of both the upper and the lower YBCO thin films is higher than about 86 K.

In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.

A method to design one-dimensional cellular arrays to be used as TPG circuits of BIST is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximum cycles are derived based on fast parallel implementations of LFSRs.

Transition coverage has been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-stage LFSR, and one-dimensional cellular automata (CAs) as TPG circuits and such sample circuits as balanced NAND tree and some ISCAS '85 benchmark circuits as CUTs. It was found that CAs which are designed so as to apply exhaustive transitions to any 3-dimensional subspaces can detect high rate of stuck-open faults. Influence of hazards of decreasing the fault coverage is also mentioned.

A method to analyze two-pattern test capabilities of autonomous test pattern generator (TPG) circuits for use in built-in self-testing are described. The TPG circuits considered here include arbitrary autonomous linear sequential circuits in which outputs are directly fed out from delay elements. Based on the transition matrix of a circuit, it is shown that the number of distinct transitions in a subspace of state variables can be obtained from rank of the submatrix. The two-pattern test capabilities of LFSRs, cellular automata, and their fast parallel implementation are investigated using the transition coverage as a metric. The relationships with dual circuits and reciprocal circuits are also mentioned.