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[Keyword] crystalline silicon(6hit)

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  • An Advanced 405-nm Laser Diode Crystallization Method of a-Si Film for Fabricating Microcrystalline-Si TFTs Open Access

    Kiyoshi MORIMOTO  Nobuyasu SUZUKI  Kazuhiko YAMANAKA  Masaaki YURI  Janet MILLIEZ  Xinbing LIU  

     
    INVITED PAPER

      Vol:
    E94-C No:11
      Page(s):
    1733-1738

    This report describes a crystallization method we developed for amorphous (a)-Si film by using 405-nm laser diodes (LDs). The proposed method has been used to fabricate bottom gate (BG) microcrystalline (µc)-Si TFTs for the first time. A µc-Si film with high crystallinity was produced and high-performance BG µc-Si TFTs with a field effect mobility of 3.6 cm2/Vs and a current on/off ratio exceeding 108 were successfully demonstrated. To determine the advantages of a 405-nm wavelength, a heat flow simulation was performed with full consideration of light interference effects. Among commercially available solid-state lasers and LDs with wavelengths having relatively high optical absorption coefficients for a-Si, three (405, 445, and 532 nm) were used in the simulation for comparison. Results demonstrated that wavelength is a crucial factor for the uniformity, efficiency, and process margin in a-Si crystallization for BG µc-Si TFTs. The 405-nm wavelength had the best simulation results. In addition, the maximum temperature profile on the gate electrode through the simulation well explained the actual crystallinity distributions of the µc-Si films.

  • Effects of Rapid Thermal Annealing on Poly-Si TFT with Different Gate Oxide Thickness

    Ching-Lin FAN  Yi-Yan LIN  Yan-Hang YANG  Hung-Che CHEN  

     
    LETTER-Electronic Displays

      Vol:
    E93-C No:1
      Page(s):
    151-153

    The electrical properties of poly-Si thin film transistors (TFTs) using rapid thermal annealing with various gate oxide thicknesses were studied in this work. It was found that Poly-Si TFT electrical characteristics with the thinnest gate oxide thickness after RTA treatment exhibits the largest performance improvement compared to TFT with thick oxide as a result of the increased incorporated amounts of the nitrogen and oxygen. Thus, the combined effects can maintain the advantages and avoid the disadvantages of scaled-down oxide, which is suitable for small-to-medium display mass production.

  • The Nature of Metallic Contamination on Various Silicon Substrates

    Geun-Min CHOI  Hiroshi MORITA  Jong-Soo KIM  Tadahiro OHMI  

     
    PAPER-Semiconductor Materials and Devices

      Vol:
    E82-C No:10
      Page(s):
    1839-1845

    The growth behavior of copper particle on crystalline and amorphous silicon surfaces has been investigated. The study reveals that the growth behavior of copper particle depends on the substrate condition. When samples are intentionally contaminated in ultrapure water, both crystalline and amorphous silicon surfaces show no difference in their contamination levels. However, copper particles were not observed on an amorphous silicon surface except dipping in dilute CuCl2 solution. The copper concentration on an amorphous silicon surface after dipping in a 0.5% HF solution is similar to the level after contaminating in ultrapure water. The copper contamination level on a crystalline silicon surface, except from CuCl2 solution, decreased two orders of magnitude as compared with ultrapure water. The copper impurity level on crystalline silicon surface was reduced by two orders by cleaning in a sulfuric acid-hydrogen peroxide mixture. The sulfuric acid-hydrogen peroxide mixture cleaning was not effective on an amorphous silicon surface. When native oxide pre-existed on an amorphous silicon surface before contamination, however, the sulfuric acid-hydrogen peroxide mixture cleaning was effective for removing copper impurity. Our results suggest that copper contamination on an amorphous silicon surface have the characteristics of bonding directly with silicon and/or existing in the native oxide, in contrast with the situation on crystalline silicon surface. After contamination with 1000 ppm copper in CuF2 solution, the etch rate of an amorphous silicon film in a 0.5% HF solution was approximately one order of magnitude faster than that of crystalline silicon. This is attributed to the difference in crystalline structure between crystalline silicon and amorphous silicon.

  • Visible Light Emission from Nanocrystalline Silicon Embedded in CaF2 Layers on Si(111)

    Masahiro WATANABE  Fumitaka IIZUKA  Masahiro ASADA  

     
    PAPER

      Vol:
    E79-C No:11
      Page(s):
    1562-1567

    We report on the formation technique and the first observation of visible light emission from silicon nanoparticles (<10nm) embedded in CaF22 Iayers grown on Si(111) substrates by using codeposition of Si and CaF2. It is shown that the size and density of silicon particles embedded in the CaF2 layer can be controlled by varying the substrate temperature and the evaporation rates of CaF2 and Si. The photoluminescence (PL) spectra of Si nanoparticles embedded in CaF2 thin films were investigated. The blue or green light emissions obtained using a He-Cd laser (λ=325nm) could be seen with the naked eye even at room temperature for the first time. It is shown that the PL intensity strongly depends on growth conditions such as the Si:CaF2 flux ratio and the growth temperature. The PL spectra were also changed by in situ annealing process. These phenomena can be explained qualitatively by the quantum size effect of Si nanoparticles embedded in CaF2 barriers.

  • Diffusion of Phosphorus in Poly/Single Crystalline Silicon

    Hideaki FUJIWARA  Hideharu NAGASAWA  Atsuhiro NISHIDA  Koji SUZUKI  Kazunobu MAMENO  Kiyoshi YONEDA  

     
    PAPER

      Vol:
    E75-C No:9
      Page(s):
    995-1000

    Diffusion of phosphorus impurities from a polycrystalline silicon films into a silicon substrate was investigated as a function of the mean concentration of phosphorus in a polycrystalline silicon film at the first diffusion stage. We presented that good control of the redistribution of implanted phosphorus impurities was possible by optimizing the normalized dose, which is the value: [the total dose of phosphorus impurities]/[the polycrystalline silicon film thickness], in the case of samples both with and without an arsenic doped layers. In the range where the normalized dose was less than 1.52.51020 cm-3, deeper junctions were formed in samples with an arsenic doped layer. In the range where the normalized dose was more than 1.52.51020 cm-3, however, deeper junctions were formed in samples without any arsenic doped layer rather than in samples with an arsenic doped layer. These results mean that formation of the junction in the device structure where a high concentration phosphorus doped polysilicon layer is stacked on to the high concentration arsenic layer embeded at the surface of the substrate can be restricted by optimizing the normalized dose. Moreover, a trade-off relationship between suppressing phosphorus diffusion and maintaining low contact resistance against normalized doses was also observed.

  • Microcrystalline Silicon in Oxide Matrix Prepared from Partial Oxidation of Anodized Porous Silicon

    Toshimichi OHTA  Osamu ARAKAKI  Toshimichi ITO  Akio HIRAKI  

     
    PAPER

      Vol:
    E75-C No:9
      Page(s):
    1025-1030

    Microcrystalline silicon embedded in silicon oxide has been prepared by means of a wet oxidation of porous silicon (PS) anodically produced from degenerate Si wafers in a HF solution. As the oxidation proceeded, optical absorptions of the PS specimen in the visible light region shifted obviously to the higher energy side. Visible light emission from the oxidized specimen was observed at room temperature with photoexcitation by a He-Cd laser while the as-prepared specimen emitted no visible lights. These results are discussed in relation to the quantum size effect of the microcrystalline silicon confined in the oxide matrix as well as visible emissions from as-prepared specimens produced from non-degenerate Si wafers.