This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

Recessed-gate DMTs (doped-channel hetero-MISFETs) with i-AlGaAs/n-GaAs structure and pseudomorphic i-AlGaAs/n-InGaAs/i-GaAs structure have been developed. Broad plateaus in gm and fT provide evidence that the DMTs make the devices suitable for high-speed large-signal operation. GaAs DMTs with 0.35 µm-length have gate turn on voltage of 0.7 V, maximum transconductance of 320 mS/mm and fT of 41 GHz. Pseudomorphic DMTs have gate turn on voltage of 0.9 V, maximum transconductance of 320 mS/mm, fT of 42 GHz and have the enhanced advantages of high current drivability and large gate swing. Further more, with the use of the recessed-gate DMTs, a high-speed laser driver IC for multi-Gb/s optical communication systems are demonstrated. This laser driver IC operates at 10 Gb/s with rise and fall times as fast as 40 psec, and it can drive up to 60 mA into a 25 Ω load.

A feed-forward (FF) BiNMOS driver that combines a multi-stage CMOS inverter and a bipolar emitter-follower transistor is proposed as a low-voltage BiCMOS driver. High-speed and low-voltage operation is made possible by a multi-stage inverter and feed-forward control from the pre-stage inverters to the bipolar emitter-follower. Two key factors determining the driver delay time, output load capacitance and wiring resistance, are described and analyzed in detail. Experiments with a gate-chains test chip fabricated with 0.5-µm BiCMOS technology confirm the low-voltage operation of the FF-BiNMOS driver. Applications of the new driver to a BiCMOS SRAM are also described.

We have successfully developed an optical receiver and a laser driver circuit which were implemented with 0.35 µm GaAs JFETs (junction Field Effect Transistors). The 0.35 µm GaAs. JFET had the typical transconductance of 480 mS/mm with small drain conductance. An interdigit MSM (Metal Semiconductor Metal) -type photodetector and the JFETs were monolithically integrated on a GaAs substrate for the optical receiver. The fabricated optical receiver demonstrated Gb/s operation with a very low power consumption of 8.2 mW. The laser driver circuit operated at up to 4.0 Gb/s.