We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.

We developed a compact, 16-channel integrated optical subscriber module for one-fiber bi-directional optical access systems. They can support more subscribers in a limited mounting space. For ultimate compactness, we created 8-channel integrated super-compact optical modules, 4-channel integrated limiting amplifiers, and 4-channel integrated LD drivers for Fast Ethernet. We introduce a new simulation method to analyze the electrical crosstalk that degrades sensitivity of the optical module. A new IC architecture is applied to reduce electrical crosstalk. We manufactured the optical subscriber module with these optical modules and ICs. Experiments confirm that the module offers a sensitivity of -27.3 dBm under 16-channel 125 Mbit/s simultaneous operation.

A novel multi-phase charge-sharing technique is proposed for the dot-inversion method to reduce AC power consumption of the TFT-LCD column driver without requiring any external capacitor for charge conservation. Simple and easy-to-control circuitry is applied in the proposed method, and the power saving efficiency depends on number of charge phases. Increasing the number of charge phases, the saving power efficiency is also raised. Excluding power dissipation of switches, the power saving efficiency is up to 75% theoretically with infinite phases. For previous work, the maximum power saving efficient is 50% without external capacitor. The HSPICE simulation results including power dissipation of all switches show that the proposed method with seven charge phases (eight-column lines as one group) decreases the power consumption of 23-68% and 10-18%, respectively, compared with original circuit (without any low-power scheme) and previous low-power charge-recycling works.

This paper describes a 51.2 GOPS video recognition processor that provides a cost effective device solution for vision-based intelligent cruise control (ICC) applications. By integrating 128 4-way VLIW (Very Low Instruction Word) processing elements and operating at 100 MHz, the processor achieves to provide a computation power enough for a weather robust lane mark and vehicle detection function written in a high level programming language, to run in video rate, while at the same time it satisfies power efficiency requirements of an in-vehicle LSI. Basing on four basic parallel methods and a software environment including an optimizing compiler of an extended C language and video-based GUI tools, efficient development of real-time video recognition applications that effectively utilize the 128 processing elements are facilitated. Benchmark results show that, this processor can provide a four times better performance compared with a 2.4 GHz general purpose micro-processor.

We report in this paper, the performance of AlGaN/GaN HFETs in the context of high power, low noise and high temperature operations, along with a comparison of their characteristics with other conventional technologies. Finally, a single stage modulator driver for long haul optical communications is presented as an example of application of the GaN-based devices high power handling capabilities.

It is very difficult to simultaneously achieve power and cost reductions in address-driver circuits of a plasma-display panel (PDP) unit in which an energy-recovery scheme utilizing the resonance of a series-connected inductor and electrode parasitic capacitors is used. This is because an increase in parasitic capacitance and high-speed circuit operation become necessary as the display panel becomes larger in size and higher in resolution. In particular, low-power operation of address-driver ICs is key to avoiding the installation of heat sinks on the ICs. We propose herein new power-dispersion methods that can greatly reduce the power dissipation of address-driver ICs even when large parasitic capacitance is driven at high speed. The proposed methods enable a reduction in the power dissipation of address-driver ICs without deteriorating the operational speed by dispersing their powers into external resistors, and by supplying power to address-driver ICs in two voltage steps during both rising and falling time intervals when the address changes. Our results indicate that the power dissipation of address-driver ICs and the total cost of the address drive unit of a plasma-display panel can be reduced to 29% and 53%, respectively, compared with those of the ICs and the unit that are driven by the conventional address-driving method.

In this letter, we propose new driving methods for designing a driver independent of the current property of Organic Light Emitting Diodes (OLED) displays. The proposed methods are the Look-Up Table (LUT) and the Pulse Width Modulation (PWM). The LUT is used to handle the amount of the current for driving the OLED display panel and the PWM is applied to represent the gray scale on the OLED display panel. In particular, the proposed methods are used for the manufacturing of 1.8" 128 128 dot passive matrix OLED display panel. The designed circuit was fabricated using 0.6 µm, 2-poly, 3-metal CMOS process and applied to the Personal Communication System (PCS) phone successfully.

In this paper a new MOS charge pump architecture is presented, where a clock generator is used in each pump stage of the charge pump circuit to elevate voltage exponentially with stages. This charge pump with a clock level shifter is designed to run at an optimized operation frequency, which can make an excellent compromise between the rise time and the dynamic power dissipation. With less stages than the linear-cascade circuit, the power dissipation and the area of the novel charge pump circuit are markedly decreased. The simulating comparison results based on 1.2 µm CMOS, p-substrate double-poly double-metal process parameters show that the nonlinear charge pump with a high pumping efficiency can supply a steady 1 mA, 16 v output for portable LCDs.

An LCD Driver IC includes more than 300 buffer amplifiers on a single chip. The phase compensation capacitors (on-chip Miller capacitors) for the amplifiers are more than 1000 pF and occupy a large chip area. This paper describes a two-gain-stage amplifier in which an on-chip Miller capacitor is not used for phase compensation in an LCD Driver IC. In the proposed amplifier, phase compensation is achieved only by a newly introduced zero, which is formed by the load capacitance and a phase compensation resistor connected between the output of the amplifier and the capacitive load. Designs of the phase compensation resistor and the amplifier before compensation are discussed, considering a typical load capacitance range. The test chip was fabricated. The newly introduced zero successfully stabilized the amplifier. The chip area for the amplifier was reduced by 30-40%, compared with our previously reported one. The current consumption of the amplifier was only 5 µA. The experimental results of the fabricated test chip support that the proposed amplifier is suitable to an LCD driver IC with a smaller chip area.

This paper proposes a compact, low-power, and rail-to-rail class-B output buffer for driving the large column line capacitance of LCDs. The comparator used as a nonlinear element in feedback path is modified from the current-mirror amplifier, which has area and power advantages. The output buffer was realized in a 0.35 m CMOS process. The active area of the buffer is 8673.5 m2. With a 3.3 V supply, the measured quiescent current is 7.4 A. The settling time for 0.05-3.25 V swing to within 0.2% is 8 s.

This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/D-As) suitable for 2.4-GHz and 5.2-GHz short-range wireless applications. The ICs are fabricated in a 0.18 µm bulk CMOS which has no extra processing steps for enhancing the RF performance. The successful use of the current-reuse topology and interdigitated capacitors (IDCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in the bulk CMOS leading to large RF substrate and conductor losses. The main measurement results of the two LN/D-As are as follows: a 3.8-dB noise figure (NF) and a 10.1-dB gain under the conditions of 1.8 V and 6 mA, a 3.4-dBm 1-dB gain compressed output power (P1dB) for a 2.4-V voltage supply and a 13-mA operating current for the 2.4-GHz LN/D-A, and a 4.9-dB NF and an 11.1-dB gain with a 1.8 V and 10 mA supply condition, a 2.3-dBm P1dB at 2.4 V and 16 mA for the 5.2-GHz LN/D-A. Both MMICs are suited for low-noise amplifiers and driver amplifiers in 2.4-GHz and 5.2-GHz low-cost, low-power wireless systems such as Bluetooth and hiperLAN.

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

A new CMOS DC voltage doubler with nonoverlapping switching control is proposed, in order to eliminate the dynamic current loss during switching as well as the threshold voltage drop of the serial switches. The simulated results at 1.5 V show that the maximum power efficiency is improved with about 30%, whereas the efficiency in the low output current region is larger than 5 times compared to the conventional voltage doublers. This proposed CMOS DC voltage doubler can be used as a VPP generator of low voltage DRAM's.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

A new output driver design called modified asymmetrical slew rate (MASR) output driver was proposed to reduce the simultaneous switching noise without sacrificing switching speed, for high speed and heavy loading applications. The driving capability of the output driver was designed to sink/source 64 mA current @ VOL/VOH = 0.4 V/4.6 V, with 66 pF and 50 Ω loading. When four drivers switch simultaneously, the ground bounce was design to be less than 0.8 V. The performances of the conventional, controlled slew rate (CSR), and MASR output drivers were analyzed by computer simulation. These three types of drivers were implemented with a 0.8 µm CMOS process. The measured ground bounce of the conventional driver is 1.22 V, while the ground bounce of the MASR driver is reduced to 0.72 V. The propagation delays of the conventional and MASR drivers are the same. The performance of the MASR driver is better than that of the CSR driver in all aspects.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.

This report describes AlGaAs/GaAs HBT ICs for 20-Gb/s optical transmission, the preamplifier and optical modulator driver circuits, and those ICs for 10-Gb/s clock extraction circuits, the rectifier and phase shifter circuits. These ICs were fabricated using our developed hetero guard-ring fully self-aligned HBT (HG-FST) fabrication process. The Pt-Ti-Pt-Au multimetal system was also used as a base ohmic metal to reduce base contact resistance, and a high fmax of 105 GHz was obtained. Good results in the HBT IC microwave performances were achieved from the on-wafer measurements. The preamplifiers exhibited the broad bandwidth of 20. 9 GHz. The optical modulator driver performed a sufficiently large output-voltage swing of 4-VP-P at a 20-Gb/s data rate. The rectifier and the phase shifter circuits achieved good operations at 10-Gb/s. These results suggest that these HBT ICs can be applied to 20-Gb/s optical transmission and 10-Gb/s clock extraction systems.

A current controlled CMOS output driver was designed by using a temperature-insensitive reference current generator. It eliminates the need for overdesign of the driver transistor size to meet the delay specification at high temperature. Comparison with the conventional CMOS output driver with the same transistor size showed that the ground bounce noise was reduced by 2.5 times and the delay time was increased by 1.4 times, at 25 for 50pF load. The temperature variations of the DC pull-up and pull-down currents of the new output driver were 4% within the temperature range from -15 to 125 compared to the variations of 40 and 60% for pull-up and pull-down respectively for the conventional output driver. The temperature insensitivity of the reference current generator was achieved by multiplying two current components. one which is proportional to mobility and the other which is inversely proportional to mobility, by using a CMOS square root circuit. The temperature variation of the DC output current of the reference current generator alone was 0.77% within the entire temperature range from -15 to 125.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

A polarity-convertible driver is necessary as a basic component of several Josephson random access memories. This driver must be able to inject a current having positive or negative polarity into a load transmission line such as a word or bit line of the RAM. In this paper, we propose a resistor coupled Josephson polarity-convertible driver which is highly sensitive to input signals and has a wide operating margin. The driver consists of several Josephson junctions and several resistors. The input signal is directly injected to the driver through the resistors. The circuit design is discussed on the operating principle of the driver. The driver is fabricated by 1.5 µm Nb technology with Nb/AlOx/Nb Josephson junctions, two layer Nb wirings, an Nb ground plane, Mo resistors, and SiO2 insulators. The Nb/AlOx/Nb Josephson junctions are fabricated using technology refined for sub-micron size junctions. The insulators between wirings are formed using bias sputtering technique to obtain good step coverage. The driver circuit size is 53 µm34 µm. Measurements are carried out at 10 kHz to quasistatically test the polarity-convertible function and the operating margin of the driver. Proper polarity-convertible operation is confirmed for a large operating bias margin of 70% at a fairly small input current of 0.3 mA.