Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)B-SbEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)B-SbEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.

Semiconductor memories are highly vulnerable to adjacent double bit errors for two reasons: 1) The bombardment of strong radioactive particles such as cosmic particles on DRAM chips and data bit lines. 2) The coupling noise in recent high density DRAM chips due to the wiring capacitance between two adjacent data bit lines. In addition, byte errors which result from entire chip failures are also a source of concern. Under this situation, codes capable of correcting adjacent double bit errors and simultaneously detecting single byte errors are suitable for application in semiconductor memory systems. This paper proposes two classes of codes called Adjacent Double bit Error Correcting-Single b-bit Byte Error Detecting (ADEC-SbED) codes and Adjacent Double bit within a b-bit byte Error Correcting-Single b-bit byte Error Detecting ((ADEC)b-SbED) codes. For the practical case where byte length is 4 bits, the proposed codes require at most one extra check bit than their bounds. Furthermore, the number check bits required by the proposed (ADEC)4-S4ED code is same as that of the well known SEC-DED code for practical information bit lengths such as 64, 128, 256, etc.

Quantum cryptography has two advantages in comparison with conventional cryptography: one is that its security is guaranteed by a fundamental physical law, and the other is that it can detect eavesdropping. In this paper, we focus on an experimental realization of quantum cryptography as a total security system. To realize this, we adopt an interferometric optical system using Faraday mirror and improve its optical system. We also utilize semiconductor laser at a short wavelength (830 nm). As a result, we have successfully implemented quantum cryptosystem including error correction and privacy amplification. We confirmed that key distribution was performed at a rate of 1.1 kbps with a 1.7% QBER (quantum bit error rate) over a distance of 200 m (optical fiber). We also show our experimental results over a distance of 1 km (optical fiber) at a rate of 0.76 kbps.

Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.

Deterministic execution testing has been considered a promising way for concurrent program testing because of its ability to replay a program's execution. Since, however, deterministic execution requires that a synchronization event sequence to be replayed be feasible and valid, it is not directly applicable to a situation in which synchronization sequences, being valid but infeasible, are taken into account. Resolving this problem is very important because a program may still meet its specification although the feasibility of all valid sequences is not satisfied. In this paper, we present a new approach to deterministic execution for testing concurrent systems. The proposed approach makes use of the notion of event independence and constructs an automation which accepts all the sequences semantically equivalent to a given event sequence to be replayed. Consequently, we can allow a program to be executed according to event sequences other than the given (possible infeasible) sequence if they can be accepted by the automation.

This paper treats the data routing problem for fault-tolerant systolic arrays based on Triple Modular Redundancy (TMR) in mixed spatial-temporal domain. The number of logical links required in TMR systolic array is basically 9 times larger than the one for corresponding non-fault-tolerant systolic array. The link sharing is a promising method for reducing the number of physical links, which may, however, degrade the fault tolerance of TMR system. This paper proposes several robust data-routing and resource-sharing (plural data transfers share a physical link, or a data transfer and a computational task share a PE as a relay node for the former and as a processor for the latter), by which certain classes of fault tolerant property will be guaranteed. A stage and a dominated set are introduced to characterize the features of routing/resource-sharing in TMR systems, and conditions on the dominated set and their resultant fault-tolerant properties are derived.

Reversible variable length codes (RVLCs), which make instantaneous decoding possible in both forward and backward directions, are exploited to code data stream in noisy enviroments. Because there is no redundancy in code words of RVLCs, RVLCs are suitable for very low bit-rate video coding. Golomb-Rice code, one of variable length code for infinite number of symbols, is widely used to encode exponentially distributed non-negative integers. We propose a reversible variable length code by modifying Golomb-Rice code, which is called parity check reversible Golomb-Rice code and abbreviated to P-RGR code. P-RGR code has the same code length distribution as GR code but can detect one-bit error in any arbitrary position of the code stream. The sets of P-RGR code words in both directions are identical so that they can be constructed by nearly the same algorithm. Furthermore, this paper also gives a general construction method for all instantaneously decodable RGR codes.

Tree-based approach has been proven to be most scalable for one-to-many reliable multicast. It efficiently combines distributed recovery with local recovery over a logical tree of the sender and receivers. It has also been known that the performance of the tree-based protocols heavily depends upon the quality of the logical tree. In this paper, we propose an end-to-end scheme to further enhance the scalability of the tree-based approach. By exchanging packet loss information observed at the end hosts, the scheme constructs and maintains a logical tree congruent with the underlying multicast routing tree even in the presence of session membership and multicast route changes. The scheme also groups the tree nodes and assigns separate multicast addresses to them in order to enable efficient multicast retransmission for reducing both delay and exposure. We compare the proposed scheme with Tree-based Multicast Transport Protocol (TMTP), a static tree-based protocol. Extensive simulations up to 300 node sessions reveal that the proposed scheme reduces implosion and exposure more than 20% and 50%, respectively. The results also indicate that the scheme is highly scalable such that the improvement gets more significant as the size of the session increases.

Near-optimality of subcodes of the cyclic Hamming codes is demonstrated on the binary additive channel whose noise process is the two-state homogeneous Markov chain, which is a model of bursty communication channels.

We study the reliability functions or the minimum r-achievable rates of the lossless coding for the general sources in the sense of Han-Verdu, where r means the exponent of the error probability. Han has obtained formulas for the minimum r-achievable rates of the general sources. Our aim is to give alternative expressions for the minimum r-achievable rates. Our result seems to be a natural extension of the known results for the stationary memoryless sources and Markov sources.

Most of the image restoration filters proposed so far include parameters that control the restoration properties. For bringing out the optimal restoration performance, these parameters should be determined so as to minimize a certain error measure such as the mean squared error (MSE) between the restored image and original image. However, this is not generally possible since the unknown original image itself is required for evaluating MSE. In this paper, we derive an estimator of MSE called the subspace information criterion (SIC), and propose determining the parameter values so that SIC is minimized. For any linear filter, SIC gives an unbiased estimate of the expected MSE over the noise. Therefore, the proposed method is valid for any linear filter. Computer simulations with the moving-average filter demonstrate that SIC gives a very accurate estimate of MSE in various situations, and the proposed procedure actually gives the optimal parameter values that minimize MSE.

The design of artificial neural networks (ANNs) through simulated evolution has been investigated for many years. The use of genetic algorithms (GAs) for such evolution suffers a prominent problem known as the permutation problem or the competing convention problem. This paper proposes a new crossover operator, which we call the selected node crossover (SNX), to overcome the permutation problem of GAs for evolving ANNs. A GA-based evolutionary system (GANet) using the SNX for evolving three layered feedforward ANNs architecture with weight learning is described. GANet uses one crossover and one mutation operators sequentially. If the first operator is successful then the second operator is not applied. GANet is less dependent on user-defined control parameters than the conventional evolutionary methods. GANet is applied to a variety of benchmarks including large (26 class) to small (2 class) classification problems. The results show that GANet can produce compact ANN architectures with small classification errors.

New method for deriving the bit error rate (BER) of the BPSK signal in the cochannel interference is proposed, which utilizes the eye pattern of the interference signal, and is different from the conventional method based on the conversion of the interference components to thermal noise. The validity of the proposed derivation method is quantitatively evaluated in terms of the BER performance and is confirmed by comparing with the results obtained by the computer simulation.

This paper proposes a 2.6 GHz low cost DBF array antenna system and reports its evaluation based on our experimental results. The proposed system is partially constructed by digital devices for the simplification of hardware, and employs some techniques for improving the resolution. The system is evaluated through the DOA estimation by the MUSIC algorithm inside a radio anechoic chamber. As a result, we found that the proposed system estimates the DOA with the highest accuracy at which MUSIC algorithm can perform. Moreover, this paper discusses the estimation errors. We also found that the estimation error is particularly affected from the inaccurate element interval.

This paper presents a new approach to modeling speech spectra and pitch for text-independent speaker identification using Gaussian mixture models based on multi-space probability distribution (MSD-GMM). MSD-GMM allows us to model continuous pitch values of voiced frames and discrete symbols for unvoiced frames in a unified framework. Spectral and pitch features are jointly modeled by a two-stream MSD-GMM. We derive maximum likelihood (ML) estimation formulae and minimum classification error (MCE) training procedure for MSD-GMM parameters. The MSD-GMM speaker models are evaluated for text-independent speaker identification tasks. The experimental results show that the MSD-GMM can efficiently model spectral and pitch features of each speaker and outperforms conventional speaker models. The results also demonstrate the utility of the MCE training of the MSD-GMM parameters and the robustness for the inter-session variability.

To improve the throughput efficiencies of ARQ protocols over a high random packet-error channel, contiguous multiple copy-transmission (CMCT) strategy for which each packet is (re-)transmitted by sending its multiple copies in contiguous slots has been used so far. However, in burst error environments, all copies may be damaged in an error burst resultting the performance degradation of CMCT. To cope with this situation, we propose, in this paper, a new strategy called intermittent multiple copy-transmission (IMCT) whereby multiple copies are sent at a fixed interval. The throughput efficiency of go-back-N ARQ using CMCT or IMCT is analyzed and considered under a two-state Markov channel model expressing burst error property of a channel. As a result, it is shown that (i) the degree of improvement of throughput efficiency by CMCT or IMCT depends on the degree of error burst and (ii) the proposed IMCT can improve the throughput efficiency of go-back-N ARQ for high and burst error channels.

We present a new family of algorithms that solve the bias problem in the equation-error based adaptive infinite impulse response (IIR) filtering. A novel constraint, called the constant-norm constraint, unifies the quadratic constraint and the monic one. By imposing the monic constraint on the mean square error (MSE) optimization, the merits of both constraints are inherited and the shortcomings are overcome. A new cost function based on the constant-norm constraint and Lagrange multiplier is defined. Minimizing the cost function gives birth to a new family of bias-free adaptive IIR filtering algorithms. For example, two efficient algorithms belonging to the family are proposed. The analysis of the stationary points is presented to show that the proposed methods can indeed produce bias-free parameter estimates in the presence of white noise. The simulation results demonstrate that the proposed methods indeed produce unbiased parameter estimation, while being simple both in computation and implementation.

A schedule for a parallel program is said to be 1-fault-secure if a system that uses the schedule can either produce correct output for the program or detect the presence of any faults in a single processor. Although several fault-secure scheduling algorithms have been proposed, they can all only be applied to a class of tree-structured task graphs with a uniform computation cost. Besides, they assume a stringent error model, called the redeemable error model, that considers extremely unlikely cases. In this paper, we first propose two new plausible error models which restrict the manner of error propagation. Then we present three fault-secure scheduling algorithms, one for each of the three models. Unlike previous algorithms, the proposed algorithms can deal with any task graphs with arbitrary computation and communication costs. Through experiments, we evaluate these algorithms and study the impact of the error models on the lengths of fault-secure schedules.

In the wireless asynchronous transfer mode (ATM) networks, a custom data link control (DLC) layer protocol with stronger error correction ability is needed for mitigating the affect of radio channel errors. This paper applies punctured turbo code schemes to the protection of the header and various payloads in wireless ATM cell, which are realized by the combination of programmable interleaving and puncturing. Their performance is analyzed for Rayleigh fading channel, which shows more significant reduction in cell loss rate (CLR) than the previous systems. Our proposal also provides good balance designs for CLR and the payload bit error rate (BER), and offers potential for future evolutionary improvement of the wireless ATM coding scheme.

The hardware implementation of a proposed high dimensional discrete torus knot code was successfully realized on an ASIC chip. The code has been worked on for more than a decade since then at Aichi Prefectural University and Nagoya Institutes of Technology, both in Nagoya, Japan. The hardware operation showed the ability to correct the errors about five to ten times the burst length, compared to the conventional codes, as expected from the code configuration and theory. The result in random error correction was also excellent, especially at a severely degraded error rate range of one hundredth to one tenth, and also for high grade characteristic exceeding 10-6. The operation was quite stable at the worst bit error rate and realized a high speed up to 50 Mbps, since the coder-decoder configuration consisted merely of an assemblage of parity check code and hardware circuitry with no critical loop path. The hardware architecture has a unique configuration and is suitable for large scale ASIC design. The developed code can be utilized for wider applications such as mobile computing and qualified digital communications, since the code will be expected to work well in both degraded and high grade channel situations.