Cross sections that cause single event upsets by heavy ions are sensitive to doping concentration in the source and drain regions, and the structure of the raised source and drain regions especially in FDSOI. Due to the parasitic bipolar effect (PBE), radiation-hardened flip flops with stacked transistors in FDSOI tend to have soft errors, which is consistent with measurement results by heavy-ion irradiation. Device-simulation results in this study show that the cross section is proportional to the silicon thickness of the raised layer and inversely proportional to the doping concentration in the drain. Increasing the doping concentration in the source and drain region enhance the Auger recombination of carriers there and suppresses the parasitic bipolar effect. PBE is also suppressed by decreasing the silicon thickness of the raised layer. Cgg-Vgs and Ids-Vgs characteristics change smaller than soft error tolerance change. Soft error tolerance can be effectively optimized by using these two determinants with only a small impact on transistor characteristics.

Soft error jeopardizes the reliability of semiconductor devices, especially those working at low voltage. In recent years, silicon-on-thin-box (SOTB), which is a FD-SOI device, is drawing attention since it is suitable for ultra-low-voltage operation. This work evaluates the contributions of SRAM, FF and combinational circuit to chip-level soft error rate (SER) based on irradiation test results. For this evaluation, this work performed neutron irradiation test for characterizing single event transient (SET) rate of SOTB and bulk circuits at 0.5 V. Using the SBU and MCU data in SRAMs from previous work, we calculated the MBU rate with/without error correcting code (ECC) and with 1/2/4-col MUX interleaving. Combining FF error rates reported in literature, we estimated chip-level SER and each contribution to chip-level SER for embedded and high-performance processors. For both the processors, without ECC, 95% errors occur at SRAM in both SOTB and bulk chips at 0.5 V and 1.0 V, and the overall chip-level SERs of the assumed SOTB chip at 0.5 V is at least 10 x lower than that of bulk chip. On the other hand, when ECC is applied to SRAM in the SOTB chip, SEUs occurring at FFs are dominant in the high-performance processor while MBUs at SRAMs are not negligible in the bulk embedded chips.

In this paper, we propose the novel Dynamic Feedback (DF-) MCML technique for high-speed and high-gain MCML type latch. The concept of the proposed DF-MCML technique is as follows; the output node signal is feedbacked to the input node in Sampling-Mode, and the output node is opened from the input node in Holding-Mode. It is shown by analytic theory that by this dynamic feedback sequence, both stability and sensibility of latch in Sampling-Mode is exponentially improved, and the gain of latch in Holding-Mode is drastically increased. Finally, we have numerically investigated the circuit performance of the novel DF-MCML type latch in comparison with the conventional MCML type latch by using P-Spice simulator. The maximum operation frequency of 180 nm DF-MCML type latch reaches over 20 GHz that is 2 times than the conventional MCML type latch. It is made clear that the proposed novel Dynamic Feedback MCML technique is suitable for over 10 GHz high-speed and high-gain Si ULSIs.

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

Application of microwave and millimeter-wave circuit technologies to InGaP-HBT ICs for 40-Gbps optical-transmission systems is demonstrated from two aspects. First, ICs for various important functions -- amplification of data signals, amplification, frequency doubling, and phase control of clock signals -- are successfully developed based on microwave and millimeter-wave circuit configurations mainly composed of distributed elements. A distributed amplifier exhibits ≥164-GHz gain-bandwidth product with low power consumption (PC) of 71.2 mW. A 20/40-GHz-band frequency doubler achieves wideband performance (40%) with low PC (26 mW) by integrating a high-pass filter and a buffer amplifier (as a low-pass filter). A compact 40-GHz analog phase shifter, 20- and 40-GHz-band clock amplifiers with low PC are also realized. Second, a familiar concept in microwave-circuit design is applied to a high-speed digital circuit. A new approach -- inserting impedance-transformer circuits -- to enable 'impedance matching' in digital ICs is successfully applied to a 40-Gbps decision circuit to prevent unwanted gain peaking and jitter increase caused by transmission lines without sacrificing chip size.

A novel multiple-valued transfer gate (T-gate) consisting of multiple-junction surface tunnel transistors (MJSTTs) and hetero-junction FETs (HJFETs) was developed and its operation was confirmed by both simulation and experiment. The number of the devices required to form the T-gate can be drastically reduced because of the high functionality of the MJSTT; namely only three MJSTTs and three HJFETs are required to fabricate the three-valued T-gate. This number of transistors is less than half that of a conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic functions. Furthermore, only one T-gate is needed to form a multiple-valued D-flip-flop (D-FF) circuit.