A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p+ buried layer and a low sheet-resistance extrinsic n+ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm2. Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF2-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

In this paper, the ATM Mini-Bar System (AMBS) which is a future information providing service infrastructure is proposed. The purpose of AMBS is to provide a multi-media environment in which a user can (1) select and get quickly any needed information, in low cost, at any time, among very large amount of different media information provided by a variety of providers, (2) be charged only for the information which is selected and used, (3) edit or process informations into users' individually requested style or format before using them. The basic concept and configurations of AMBS are also addressed. This system is basically a center-end oriented one-way information providing system. The information center broadcasts its contents to all user equipments based on a user request forecast, and every user equipment stores the delivered contents in its large storage. A user can select one's needed informations from the storage, and may edit or process them within the user equipment. The charge is only on the read informations from the storage, not on all contents in it. The key points of this system are the following three. (A) Introduction of a broadcast (or multicast) media for economical information delivery (exactly speaking, it is a predelivery which means a delivery before request) to user equipments. (B) Introduction of a 1 to 1 communication network for selective charging and control of each user equipments. (C) Introduction of the user equipment storage for Quick response to user information request in most cases with the broadcast (or multicast) information delivery media described above, Separation of information delivery speed and replay speed to increase system flexibility, Local user information processing or editing. As an example of technical solutions, a memory architecture, which is based on hierarchical architecture, is described. AMBS is expected to give some impacts to information industries because it can integrate many kinds of services into the same platform, but some standerdization items are needed to realize it.

This paper examines performance study items for ATM connections in B-ISDNs. We consider the characteristics of B-ISDN performance and describe the current status in ITU-T and the ATM Forum. On this basis, we propose a new performance framework and performance criteria. We also describe objectives for ATM cell transfer performance.

Complexity of Boolean functions satisfying the propagation criterion (PC), an extended notion of the perfect nonlinearity, is discussed on several computation models. The following topics are investigated: (i) relationships between the unateness and the degree of the PC, (ii) the inversion complexity of perfectly nonlinear Boolean functions, (iii) the formula size of Boolean functions that satisfy the PC of degree 1, (iv) the area-time-square complexity of VLSI circuits computing perfectly nonlinear Boolean functions, (v) the OBDD size perfectly nonlinear Boolean functions.

In this paper, we present a method for extracting the Japanese printed characters from unformatted document images. This research takes into account the multiple general features specific to the Japanese printed characters. In our method, these features are thought of as the constraints for the regions to be extracted within the constraint satisfaction approach. This is achieved by minimizing a constraint function estimating quantitative satisfaction of the features. Our method is applicable to all kinds of the Japanese documents because it is no need of a priori knowledge about the document layout. We have favorable experimental results for the effectiveness of this method.

In the actual sound environmental systems, it seems to be essentially difficult to exactly evaluate a whole probability distribution form of its response fluctuation, owing to various types of natural, social and human factors. We have reported a unified probability density expression in the standard expansion form of Hermite type orthonormal series taking a well-known Gaussian probability density function (abbr. p.d.f.) as the basis for generally evaluating non-Gaussian, non-linear correlation and/or non-stationary properties of the fluctuation phenomenon. However, in the real sound environment, there still remain many actual problems on the necessity of improving the above standard type probability expression for practical use. First, a central point in this paper is focused on how to find a new probabilistic theory of practically evaluating the variety and complexity of the actual random fluctuations, especially through newly introducing an equvivalence transformation toward the standard type probability expression mentioned above in the expansion form of Hermite type orthonormal series. Then, the effectiveness of the proposed theory has been confirmed experimentally too by applying it to the actual problems on the response probability evaluation of various sound insulation systems in an acoustic room.

In this paper we describe the formal conditions to detect and resolve all kinds of pipeline data hazards and propose a scheduling algorithm for pipelined instruction set processor synthesis. The algorithm deals with multi cycle operations and tries to minimize the pipeline execution cycles under a given hardware configuration with/without hardware interlock. The main feature that makes the proposed algorithm different from existing ones is the algorithm is for estimating the performance in HW/SW partitioning, with capability of handling a module library of different FUs and dealing with multi cycle operations to be implemented in software. Experimental results of application to ASIP HW/SW codesign show that the proposed algorithm is effective and considerable pipeline execution cycle reduction rates can be achieved. The time complexity of the scheduing algorithm is of O(n2) in the worst case, where n is the number of instructions in a given basic block.

It has become more important to reduce the protocol implementation costs as the functions of protocols have become more abundant. The protocol implementation tools which automatically generate a protocol program from a specification described by an FDT (Formal Description Technique) are very promising. Selecting SDL as a target FDT, we have developed an SDL-based protocol implementation tool which consists of a process scheduler and a compiler. Since the efficient SDL process execution is a key to generating the high-speed program, the scheduler is introduced. It provides the mechanism which executes SDL processes concurrently as light-weight-processes. It optimizes so that as few context switches take places as possible. The compiler converts as many kinds of SDL functions whose behaviors can be determined at compile time into programming language statements as possible. These elaborations are so successful that the tool can generate an efficient program. The OSI Transport protocol class 0 program generated by the compiler can process more than 500 packets per second on a 6MIPS workstation.

This paper deals with network performance of 64kbit/s-based services supported in an ATM network and an ATM interworking network with 64kbit/s-based networks. It first clarifies network performance issues giving a model and objectives of study and experiment. A result of computational analysis is then presented, where a cell loss ratio of an order of 10-4 or 10-5 is obtained to give a performance equivalent to that currently used as objective values in existing networks for a 64kbit/s digital level. In order to capture the impact of cell loss and associated performance for application levels, an experimental test has been carried out using typical applications. Test results show that the cell loss ratio needs to be approximately ten times better than the bit error ratio for comparable performance for application levels. A cell loss ratio of better than 10-5, or an order of 10-6 considering an interworking situation, seems to be necessary according to the test results. It is further clarified by the test that a single cell is more valuable than a multiplexed cell for providing better cell loss resilience characteristics. Although not all applications of 64kbit/s networks have been tested, it is expected that the test results can be used as guidance for considering the support of 64 kbit/s services in an ATM and interworking networks.

This paper investigates the problem of scheduling parallel tasks" with consideration of communication cost on an m-processor system, where processors are assumed to be identical and tasks being scheduled are independent such that they can run on more than one processor simultaneously. Once a task is processed in parallel, its finish time will be speeded up, but communication cost will also be incurred and should be taken into account. To find a schedule with minimum finish time for the parallel tasks scheduling problem is NP-hard. Therefore, in this paper, we will propose a heuristic algorithm for this kind of problem and derive its performance bounds for two different cases of applications, respectively.

There is a wide perception of the need for conformance and interoperability testing to ensure the interoperability of open systems. In the circumstances, we have been making efforts to establish a system for interconnectability testing, which is a type of the interoperability testing. In this paper, we discuss an interconnectability testing system, named AICTS (AIC's InterConnectability Testing System) that we have designed. We also discuss a conformance testing system, named ACTS (AIC Conformance Test System), which we developed as the first step toward building an interconnectability testing system. ACTS is capable of extensions for an interconnectability testing system.

The discrete-time short-time Fourier transform (STFT) is known as a useful tool for analyzing and synthesizing signals. This paper introduces an extention of the well-known STFT to a general form which is more suitable for high resolutional signal analysis. A channel frequency division scheme is developed for realizing arbitrary bandwidth and center frequency so as to improve resolution performance. It is based on a nonuniform filter bank structure with integer decimation and interpolation factors. A design example of the generalized STFT using symmetric windows is given.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.

We define a new framework for rewriting graphs, called a formal graph system (FGS), which is a logic program having hypergraphs instead of terms in first-order logic. We first prove that a class of graphs is generated by a hyperedge replacement grammar if and only if it is defined by an FGS of a special form called a regular FGS. In the same way as logic programs, we can define a refutation tree for an FGS. The classes of TTSP graphs and outerplanar graphs are definable by regular FGSs. Then, we consider the problem of constructing a refutation tree of a graph for these FGSs. For the FGS defining TTSP graphs, we present a refutation tree algorithm of O(log2nlogm) time with O(nm) processors on an EREW PRAM. For the FGS defining outerplanar graphs, we show that the refutation tree problem can be solved in O(log2n) time with O(nm) processors on an EREW PRAM. Here, n and m are the numbers of vertices and edges of an input graph, respectively.

In the present paper, we attempt to show that the information about input patterns must be as small as possible for improving the generalization performance under the condition that the network can produce targets with appropriate accuracy. The information is defined with respect to the hidden unit activity and we suppose that the hidden unit has a crucial role to store the information content about input patterns. The information is defined by the difference between uncertainty of the hidden unit at the initial stage of the learning and the uncertainty of the hidden unit at the final stage of the learning. After having formulated an update rule for the information minimization, we applied the method to a problem of language acquisition: the inference of the past tense forms of regular and irregular verbs. Experimental results confirmed that by our method, the information was significantly decreased and the generalization performance was greatly improved.

A permutation cipher scheme using polynomials over a field is presented. A permutation as well as substitution plays a major role in almost all conventional cryptosystems. But the security of the permutation depends on how symbols are permuted. This paper proposes the use of polynomials for the permutation and show that the scheme satisfies the following security criteria. (1) There are enough encryption keys to defend exhaustive attacks. (2) The permutation moves almost all samples into places which are different from the original places. (3) Most samples are shifted differently by different permutations. The permutation cipher scheme could be regarded as a scheme based on Reed-Solomon codes. The information symbols of the codes compose a key of the permutation cipher scheme.

The potential attenuation process of charged human body (HB) is analyzed. A two-dimensional circuit model is presented for predicting the potential attenuation characteristics of the HB charged on the floor. The theoretical equation for the HB potential is derived in the closed form in the Laplacian transformation domain, and the numerical inverse Laplace transform is used to compute it. The half-life or relaxation time of the HB potential for decay is numerically examined with respect to the electrical parameters of shoes. The experiment is also conducted for verifying the validity of the computed result.

In this paper a method of recognizing waveform based on the Discrete Wavelet Transform (DWT) presented by us is applied to detecting the K-complex in human's EEG which is a slow wave overridden by fast rhythms (called as spindle). The features of K-complex are extracted in terms of three parameters: the local maxima of the wavelet transform modulus, average slope and the number of DWT coefficients in a wave. The 4th order B-spline wavelet is selected as the wavelet basis. Two channels at different resolutions are used to detect slow wave and sleep spindle contained in the K-complex. According to the principle of the minimum distance classification the classifiers are designed in order to decide the thresholds of recognition criteria. The EEG signal containing K-complexes elicited by sound stimuli is used as pattern to train the classifiers. Compared with traditional method of waveform recognition in time domain, this method has the advantage of automatically classifying duration ranks of various waves with different frequencies. Hence, it specially is suitable to recognition of signals which are the superimposition of waves with different frequencies. The experimental results of detection of K-complexes indicate that the method is effective.

This paper describes a method of coding image sequences based on global/local motion information. The suggested method initially estimates global motion parameters and segments a target region from a given image. Then we coded background and target region by assigning more bits to the target region and less bits to background in order to reconstruct the target region with high quality. Simulations show that the suggested algorithm has better result than the existing methods, especially in the circumstances where background changes and target region is small enough compared with that of background.

In formal specification languages for parallel processes, such as CSP and LOTOS, algebraic laws for basic operators are provided that can be used to transform process expressions, and in particular, composition of processes can be calculated using these laws. Process composition can be used to simplify and improve the specification, and also to prove properties of the specification such as deadlock absence. We here test the practicality of process composition using CSP and suggest useful techniques, working in an example with nontrivial size and complexity. We emphasize that the size explosion of composed processes, caused by interleaving of the events of component processes, is a serious problem. Then we propose a technique, which we name two-way pipe, that can be used to reduce the size of the composed process, regarded as a program optimization at specification level.