In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (Vh) and high triggering voltage (Vt1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate Vt1 of 6.3 V, high Vh of 4.2 V, high normalized second breakdown current (It2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

Design of an equivalent slew-rate monolithic pulse generator using bipolar-CMOS-DMOS (BCD) technology for medical ultrasound transmitters is presented in this paper. The pulse generator employs a floating capacitive coupling level-shifter architecture to produce a high-voltage (Vpp=80V) output. The performance of equivalent slew-rate in the rising and falling edge is achieved by carefully choosing the value of coupling capacitors and the size of the final stage high-voltage MOSFETs of the pulse generator. The measured output pulses show the rising and falling time of 8.6nsec and 8.5nsec, respectively with second harmonic distortion down to -40dBc, indicating the designed pulse generator can be used for advanced ultrasonic harmonic imaging systems.

High efficiency power feeding systems are effective solutions for reducing the ICT power consumption with reducing power consumption of the ICT equipment and cooling systems. A higher voltage direct current (HVDC) power feeding system prototype was produced. This system is composed of a rectifier equipment, power distribution unit, batteries, and the ICT equipment. The configuration is similar to a -48 V DC power supply system. The output of the rectifier equipment is 100 kW, and the output voltage is 401.4 V. This paper present the configuration of the HVDC power feeding system and discuss its basic characteristics in the prototype system.

A new low voltage operation of high voltage switching technique, which is capable of reducing leakage current by an order of three compared to conventional circuits, has been developed for sub-1.8 V low voltage mobile NAND flash memory. In addition, by using the proposed high voltage switch, chip size scaling can be realized due to reduced a minimum required space between the N-wells of selected and unselected blocks for isolation. The proposed scheme is essential to achieve low power operation NAND Flash memory, especially for mobile electronics.

This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.

A charge pump circuit suitable for positive high voltage generators at sub-1.5 V range is presented. The proposed heap-pump circuit provides a high voltage generator having not only high pumping efficiency by eliminating threshold voltage drop but also simplest single phase clock scheme.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

An on-chip high voltage generator applicable to low voltage flash memory is introduced. Bootstrapped gate transfer switches of two parallel paths suppress the voltage loss due to threshold voltage drop of transfer transistors. The simulated results demonstrate that proposed circuit designed with NMOS transistors having 0.8 volt threshold voltage works like an ideal charge pump circuit near 1.0 volt range with enough current driving capability.

This paper describes an analytic method, experimental results and simulation results for self-heating in a SOI (Silicon On Insulator) high voltage MOS transistor. The new analytic method enabled the temperature-rise caused by self-heating to be measured precisely. The temperature-rise in an operating transistor was evaluated by measuring the change of the source current against the source current without the self-heating. In advance, the relation between the temperature-rise and the current change had been prepared by measuring the current decrease when the hot-chuck temperature had been changed in iso-thermal condition. By using this method, the dependence of the temperature-rise or the current decrease on the operating condition or the thermal resistance were clarified. Furthermore, these measurement results and the thermal resistance which is calculated by a FEM analysis enabled a fully coupled electrothermal device simulation to be analyzed more precisely. The dependence of the current decrease on the buried oxide thickness were also calculated.

For high frequency video signals, display monitors for personal computers are required to shift from the horizontal scanning frequency fH=15.75 kHz for conventional TV broadcasting to fH=64 to 80 kHz, which is called XGA. Shifting to high frequencies and restrictions on the withstand voltage of horizontal transistors decrease the inductance of deflection yokes, which is an obstacle in manufacturing deflection yokes. A study was undertaken on an operation to permit deflection/high voltage integrated operation while keeping the inductance of the deflection yoke high. This paper reports the results.

A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.