Throughout the paper, the nearest-neighbour (NN) interconnection of switches within a multistage interconnection network (MIN) is analysed. Three main results are obtained: (1) The switch preserving transformation of a 2-D MIN into the 1-D MIN (and vice versa) (2) The rearrangeability of the MIN and (3) The number of stages (NS) for the rearrangeable nonblocking interconnection. The analysis is extended to any dimension of the interconnected data set. The topological equivalence between 1-D MINs with NN interconnections (NN-MINs) and 1-D cellular arrays is shown.

A new algorithm, which is incorporated into the waveform relaxation analysis, for efficiently simulating the transient response of single lossy transmission lines or lossy coupled multiconductor transmission lines, terminated with arbitrary networks will be presented. This method exploits the inherent delay present in a transmission line for achieving simulation efficiency equivalent to obtaining converged waveforms with a single iteration by the conventional iterative waveform relaxation approach. To this end we propose 'line delay window partitioning' algorithm in which the simulation interval is divided into sequential windows of duration equal to the transmission line delay. This window scheme enables the computation of the reflected voltage waveforms accurately, ahead of simulation, in each window. It should be noted that the present window partitioning scheme is different from the existing window techniques which are aimed at exploiting the non–uniform convergence in different windows. In contrast, the present window technique is equivalent to achieving uniform convergence in all the windows with a single iteration. In addition our method eliminates the need to simulate the transmission line delay by the application of Branin's classical method of characteristics. Further, we describe a simple and efficient method to compute the attenuated waveforms using a particular form of lumped element model of attenuation function. Simulation examples of both single and coupled lines terminated with linear and nonlinear elements will be presented. Comparison indicates that the present method is several times faster than the previous waveform relaxation method and its accuracy is verified by the circuit simulator PSpice.

This paper presents a cost-effective network for very large ATM cross-connects. In order to develop it, we propose the delta network with expanded middle stages. This proposed network is the intermediate network between a nonblocking network and the delta network with respect to the cost of hardware and internal blocking probability. Using this network, we explore the tradeoff between the cost and internal blocking probability, and derive the optimum configuration under temporarily deviating traffic. Internal blocking occurs when input traffic temporarily deviates from its average value. However, we cannot evaluate the internal blocking probability by using conventional traffic models. In this paper, we adopt temporarily deviating traffic such that all traffic is described as the superposition of the paths which are defined by traffic parameters. As can easily be seen, the path corresponds to virtual path (VP) or virtual channel (VC). Therefore, we believe that our model describes actual traffic more exactly than conventional models do. We show that the optimum configuration is the proposed network whose expansion ratio γ=3 when the maximum number of paths that can be accommodated in one link is greater than 22. This network achieves the internal blocking probability of 10-10. As an example of this network, we show that the proposed network of size 7272 is constructed with only 40% of the hardware required by the nonblocking network.

In general, message passing multiprocessors suffer from communication overhead and shared memory multiprocessors suffer from memory contention. Also, data I/O overhead limits performance. In particular, computer vision tasks that require massive computation are strongly affected by these disadvantages. This paper proposes new parallel architectures for computer vision, a Flexibly (Tightly/Loosely) Coupled Multiprocessor (FCM) and a Flexibly Coupled Hypercube Multiprocessor (FCHM) to alleviate these problems. FCM and FCHM have a variable address space memory in which a set of neighboring memory modules can be merged into a shared memory by a dynamically partitionable topology. FCM and FCHM are based on two different topologies: reconfigurable bus and hypercube. The proposed architectures are quantitatively analyzed using computational models and parallel vision algorithms are simulated on FCM and FCHM using the Intel's Personal SuperComputer (iPSC), a hypercube multiprocessor, showing significant performance improvements over that of iPSC.

High-speed pulse propagation, up to several hundred Mbps or higher, will play an important role in telecommunication systems for B-ISDN. High-performance packaging, especially high-speed, high-throughput interconnection, is strongly required. For advanced telecommunication systems, giga-bit signal transmission has been developed at the multi-chip module level, and 300 to 600 Mbps signal transmission has been reached at the printed circuit board level. Electrical inter-cabinet interconnections of 150 to 300 Mbps have been achieved for up to several tens of meters. High-speed, high-throughput connectors are the key to achieving high-performance telecommunication packaging systems. Two technologies are extremely important. One is for high-density, high-pin-count connectors, and the other is for high-speed signal transmission connectors. The requirements for the connectors needed for advanced high-performance telecommunication systems are described. Several high-density, high-bandwidth connectors developed for high-performance packaging system are introduced.

In this paper we estimate the number of permutations realizable in fault-tolerant multistage interconnection networks designed to tolerate faults on any switching element. The Parallel Omega network and the INDRA network are representative types of fault-tolerate multistage interconnection networks designed to tolerate a single fault. In order to evaluate the enhancement in the function of network by preparing the hardware redundancy for fault-tolerance, we estimate the number of permutations realizable in fault-tolerant networks. This result enables us to set up a standard to evaluate the hardware redundancy required to tolerate multifaults from the viewpoint of the enhancement of network function. This paper concludes that in the case where the number of inputs is up to 32 the increase ratio of the number of realizable permutations is no more than 1/0.73 even if the tolerance to multifaults is prepared instead of the tolerance to a single fault.

A network system is proposed for segmenting and extracting multiple moving objects in 2D images. The system uses an interconnected neural network in which grouping factors, such as edge proximity, smoothness of edge orientatio, and smoothness of velocity perpendicular to an edge, are embedded. The system groups edges so that the network energy may be minimized, i.e. edges may be organized into perceptually plausible configuration. Experimantal results are provided to indicate the performance and noise robustness of the system in extracting objects in synthetic images.

The origin of and a method of enhancing the Optical Beam Induced Resistance Change (OBIRCH) signal for defect observation in VLSI metal interconnections is discussed based on a numerical analysis of three-dimensional thermal conduction and experimental results. The numerical analysis shows that the OBIRCH signal originates from a slight increase in the resistance of the metal line caused by laser beam heating and that its effect is influenced by the temperature of the metal layer. Both simulations and experimental results suggest that cooling the sample is preferable to detect the OBIRCH signal. The decrease in the total resistance of the metal line without any change in the amount of the resistance increase under laser illumination is found to be the main cause of the OBIRCH signal enhancement under low temperature measurement.

In this paper, we study a dynamic bandwidth control which is expected an effective use of network resources in transmitting highly bursty traffic generated by, e.g., interconnected LAN systems. First, a new LAN traffic model is proposed in which correlation of not only packet interarrival times but also packet lengths are considered. An analytic model for a LAN-ATM gateway is next introduced. It employs the dynamic bandwidth control using the proposed LAN traffic model and some performance measures are derived by it. The analytic model takes into account the probability that a bandwidth increase request may be rejected. Finally, some numerical examples are provided using the analysis method and performance comparisons between the dynamic and fixed bandwidth controls are made. As a result, it is quantitatively indicated that () if the equivalent bandwidth is used in average, the dynamic bandwidth control keeps packet and cell loss rates one to two orders lower than the fixed bandwidth control, () when the more strict QOS in terms of loss rate is requested, the dynamic bandwidth control can become more effective.

We have studied a circuit partitioning approach in the view of parallel circuit simulation on a MIMD parallel computer. In parallel circuit simulation, a circuit is partitioned into equally sized subcircuits while minimizing the number of interconnection nodes. Besides circuit partitioning time should be short enough compared with the total simulation time. From the details of circuit simulation time, we found that balancing subcircuits is critical for low parallel processing, whereas minimizing the interconnection nodes is critical for highly parallel processing. Our circuit partitioning approach consists of four steps： Grouping transistors, initial partitioning the transistor-groups, minimizing the number of interconnection nodes, and balancing the subcircuits. It is based on an algorithmic approach, and can directly control the tradeoffs between balancing subcircuits and minimizing the interconnection nodes by adjusting the parameters. We partitioned a test circuit with 3277 transistors into 4, 9, ... , 64 subcircuits, and did parallel simulations using PARACS, our parallel circuit simulator, on an AP1000 parallel computer. The circuit partitioning time was short enough-less than 3 percent of the total simulation time. The highest performance of parallel analysis using 49 processors was 16 times that of a single processor, and that for total simulation was 9 times.

A photonic inter-module connector for near-future electronic switching systems is demonstrated through the use of silica-based 88 optical switches. A small-scale switch matrix is sufficient because the near-future systems will consist of a limited number of modules. If an active module is affected by a fatal fault or accident, a stand-by module must quickly take its place. The experimental photonic inter-module connector can switch 156-Mbit/s photonic interconnections between seven subscriber-line-concentrator modules and eight circuit-switching modules.

This paper briefly reviews recent studies on free-space photonic switches, and discusses classifications, applications and technical issues to be solved. The free-space photonic switch is a switch that uses light beam interconnections based on free-space optics instead of guided-wave optics. A feature of the free-space switch is its high-density three-dimensional structure that enables compact large-scale switches to be created. In this paper, the free-space switches are classified by their various attributes such as logical network configuration, path-establishment method, number of physical stages, signal-waveform transmission form, interconnection optics and so on. The logical network configuration (topological geometry or topology) is strongly related to the advantages of the free-space switches over the guided-wave switches. The path-establishment method (path-shifting/branching-and-gating) and the number of physical stages (single-stage/multistage) are related to physical switching characteristics. Signal-waveform transmission form (analog/digital) is related to switch application. Interconnection optics (imaging system/micro-beam system) is related to the density and volume of the switching fabric. Examples of the free-space switches (single-stage, analog multistage, digital multistage and photonic ATM switches) are described. Possible applications for analog switches are subscriber-line concentrators, inter-module connectors, and switching networks for parallel or distributed computer systems. Those for digital switches include multistage space-division switches in time-division circuit-switching or packet switching systems (including asynchronous transfer mode [ATM] switching system) for both communications switching systems and parallel/distributed computer systems. Technical issues of the free-space switches (system, device, assembly technique) must be solved before creating practical systems. In particular, the assembly technique is a key issue of the free-space switches.

Beam-steering devices are attractive for spatial optical interconnections. Those devices are essential not only for fixed connecting routed optical interconnections, but for flexible connecting routed optical interconnections. The flexible connecting routed optical interconections are more powerful than the conventional fixed connecting routed ones. Structures and characteristics of beam-steering devices, a beam-scanning laser diode and a fringe-shifting laser diode, are reported for those interconnections. Using these lasers, the configurations of several optical interconnections, such as optical buses and optical data switching links as examples of fixed and flexible connecting routed optical interconnections are discussed.

The crosstalk characteristics of a long-wavelength monolithically integrated photoreceiver array are analyzed. The device consists of an array of transimpedance photoreceivers fabricated on a semi-insulating InP substrate. The distance between the photodetectors is large enough to suppress the photonic crosstalk. Therefore, the crosstalk of the device is mainly due to signal propagation from the channels through the power line shared by each channel on the chip. This crosstalk is inevitable to the photoreceiver arrays which employ common power lines. The magnitude of the crosstalk largely depends on the impedance of the power-supply circuit outside the chip. The crosstalk spectrum often has a peak and recess structure. The crosstalk peak at the edge of the operating band-width is due to the resonance characteristic of the transimpedance amplifier. The other peak and recess structures on the spectrum are due to the resonance phenomena of on-chip and off-chip capacitors and inductance on the power-supply line outside the chip. This crosstalk can be reduced by using on-chip bypass capacitance and dumping resistance. However, the resonance due to the capacitance and inductance on the power-supply circuit outside the chip can't be controlled by the on-chip components. Therefore, an optimized design for the power supply circuit outside the chip is also indispensable for suppressing crosstalk.

A transmission data format for high-speed optical parallel interconnections is proposed and a 4-channel transmitter and receiver link module operating at up to 1.2 Gb/s per channel is demonstrated. The data format features "Group Multiplexing and Coding." In this scheme, input several tens channels are multiplexed and coded in group into reduced channels, resulting in burst-mode compatible, skew-free transmission, and low power-consumption of a link module. Experiments with fabricated modules comfirm that our data coding in multichannel optical transmission is promising for use in high-speed interconnections in information and switching systems.

Via electromigration (EM) performance of aluminum based metallization (AL) systems has been investigated for vias chains of 1500-4000 vias of 1.0 micron diameter. The results show that via EM lifetime can not be enhanced by a simple increase of M2 step coverage in AL/AL vias because the EM induced voids are formed at AL/AL via interface where electrons flow from Ml to M2 even in the case of very poor M2 step coverage. The voids are induced by the boundary layer in AL/AL vias, where a temperature gradient causes discontinuity of aluminum atoms flux. The failure location is not moved though via EM lifetime can be improved by controlling stress in passivation, sputter etch removal thickness and grain size of the first metal. Next, the effect of the boundary layer are eliminated by depositing titanium under the second aluminum or depositing WSi on the first aluminum. In the both cases, via EM lifetime are improved and the failure locations are changed. Especially WSi layer suppresses the voids formation rather than titanium. Models for the failure mechanism in each metallization system are further discussed.

This paper describes the use of optical interconnections in switching systems and discusses our recent achievements in this area. Switching system interconnections are classified based on their application layers. The evolution of optical interconnections in switching systems in discussed in terms of such system requirements as cost, size, and throughput. Recent achievements are discussed: an optical inter-module connector, a free-space digital switch, and a large-capacity optically intra-connected ATM switch.

We propose an optical computing architecture called pure optical parall array logic system (P-OPALS) as an instance of sophisticated optical computing system. On the P-OPALS, high density images can be processed in parallel using the optical system with high resolving power. We point out problems on the way to develop the P-OPALS and propose logical foundation of the P-OPALS called single-input optical array logic (S-OAL) as a solution of those problems. Based on the proposed architecture, an experimental system of the P-OPALS is constructed by using three optical techniques: birefringent encoding, selectable discrete correlator, and birefringent decoding. To show processing capability of the P-OPALS, some basic parallel operations are demonstrated. The results obtained indicate that image consisting of 300 100 pixels can be processed in parallel on the experimental P-OPALS. Finally, we estimate potential capability of the P-OPALS.

In this paper, we present some novel concepts and photonic devices for use in optical interconnects. First, we review the progress of surface emitting lasers while featuring materials and performances including thresholds, power output, RIN, linewidth, and so on. Advanced technology for aiming at spontaneous emission control, photon recycling, polarization control, wavelength tuning, integration etc. will be considered. Then we touch on some other possible devices for optical interconnects. Lastly, we discuss on lightwave subsystems applying these devices and concepts.

A quantum interconnection scheme by controlling the Coulomb interaction between ballistic electrons is proposed in which 2DEG (2 dimensional electron gas) plays the role of an interconnection medium. This concept brings up new possibilities for the interconnection approach in various fields such as parallel processing, telecommunications switching, and quantum functional devices. Cross-over interconnection, address collision, and address selection in a quantum information network system were analyzed as the first step. The obtained results have shown that the interconnection probability can be controlled by the velocity and timing of the ballistic electron emission from the emitter electrode. The proposed interconnection scheme is expected to open up a new field of quantum effect integrated circuits in the 21st century.