We propose a distributed operation system platform for optical cable networks. This distributed platform is an extension of the previously proposed platform for a flexible cable network operation. The concept of the unit platform has been proposed for the distributed operation system platform. By using this concept, we discuss the system upgrade including the connection to other operation systems. We use an object-oriented software technology for designing the distributed operation system platform. The prototype system has been constructed using C++ programing language and the evaluated results are shown.

This work deals with thermal-noise modeling for silicon vertical bipolar junction transistors (BJTs) and relevant integrated circuits (ICs) operating at low currents. The two-junction BJT compact model is consistently derived from the thermal-noise generalization of the Shockley semiconductor equations developed in work which treats thermal noise as the noise associated with carrier velocity fluctuations. This model describes BJT with the Itô non-linear stochastic-differential-equation (SDE) system and is suitable for large-signal large-fluctuation analysis. It is shown that thermal noise in silicon p-n-junction diode contributes to "microplasma" noise. The above model opens way for a consistent-modeling-based design/optimization of bipolar device noise performance with the help of theory of Itô's SDEs.

In circuit partitioning for FPGAs, partitioned signal nets are connected using I/O blocks, through which signals are coming from or going to external pins. However, the number of I/O blocks per chip is relatively small compared with the number of logic-blocks, which realize logic functions, accommodated in the FPGA chip. Because of the I/O block limitation, the size of a circuit implemented on each FPGA chip is usually small, which leads to a serious decrease of logic-block utilization. It is required to utilize unused logic-blocks in terms of reducing the number of I/O blocks and realize circuits on given FPGA chips. In this paper, we propose an algorithm which partitions an initial circuit into multi-FPGA chips. The algorithm is based on recursive bi-partitioning of a circuit. In each bi-partitioning, it searches a partitioning position of a circuit such that each of partitioned subcircuits is accommodated in each FPGA chip with making the number of signal nets between chips as small as possible. Such bi-partitioning is achieved by computing a minimum cut repeatedly applying a network flow technique, and replicating logic-blocks appropriately. Since a set of logic-blocks assigned to each chip is computed separately, logic-blocks to be replicated are naturally determined. This means that the algorithm makes good use of unused logic-blocks from the viewpoint of reducing the number of signal nets between chips, i.e. the number of required I/O blocks. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with conventional algorithms.

Up to now, the only useful and well-known structural or initial-marking-based necessary and sufficient liveness conditions of Petri nets have only been those of an extended free-choice (EFC) net and its subclasses such as a free-choice (FC) net, a forward conflict free (FCF) net, a marked graph (MG), and a state machine (SM). All the above subclasses are activated only by deadlock-trap properties (i.e., real d-t properties in this paper), which mean that every minimal structural deadlock (MSDL ND=(SD, TD, FD, MoD)) in a net contains at least one live minimal structural trap (MSTR NT=(ST, TT, FT, MoT)) which is initially marked. However, the necessary and sufficient liveness conditions for EFCF, EBCF, EMGEFCFEBCF, AC (EFCFC), and the net with kindling traps NKT have recently been determined, in which each MSDL without real d-t properties was also activated by a new type of trap of trap, i.e., behavioral traps (BTRs), which are defined by introducing a virtual MSTR, a virtual maximal structural trap (virtual STR), a virtual MSDL, and a virtual maximal structural deadlock (virtual SDL) into a target MSDL. In this paper, a structural or initial-marking-based necessary and sufficient condition for local liveness (i.e., virtual deadlock-trap properties) of each MSDL ND s.t. SDST, SDST, SDST (but ND s.t. SDST is dead owing to real deadlock-trap properties) in a general Petri net N is presented by extending that in NKT. Specifically, live minimal behavioral traps (MBTRs) as well as live maximal behavioral traps (BTRs), i.e., virtual deadlock-trap properties, in a general Petri net N are characterized using the real d-t properties of each MSDL ND s.t. SDST for a general Petri net N, which were also obtained by extending the concept of return paths in NKT in connection with an MSDL which contains at least one MSTR and by using the concepts of T-cornucopias and absolute T-cornucopias in a subclass Ñ of N. In other words, BTRs are defined by introducing a virtual MSTR, a virtual STR, a virtual MSDL, and a virtual SDL into a target MSDL without real d-t properties. Additionally, a structural or initial-marking-based necessary and sufficient condition for liveness of a new subclass Nn of a general Petri net N (i.e., a general Petri net without time) is derived, and the usefulness of the obtained results is also discussed.

If a general Petri net N = (S, T, F, Mo) is transition-live under Mo, it is evident that each maximal structural deadlock SDL(D) in N as well as each minimal structural deadlock MSDL (ND) in each D is also transition-live under Mo. However, since the converse of the latter of the above is not always true, it is important to obtain the conditions for this converse to be true if we want to have a useful necessary and sufficient "initial-marking-based" or "structural" liveness condition for N. Up to now, usefull and well-known structural or initial-marking-based necessary and sufficient liveness conditions of Petri nets have only been those of an asymmetric choice (AC) net and its subclasses such as an EFC net, an FC net, an FCF net, MG, and SM. However, all the above subclasses are activated only by real or virtual deadlock-trap properties which are local liveness for each minimal deadlocks; in other words, the above topics of this paper are unconditionally satisfied in those subclasses because of their special structure of nets. In this paper, a necessary and sufficient structural liveness condition for a general Petri net N with globally structural live minimal structural deadlocks is presented as follows: The next () or () is satisfied. () N has no SDL D. () If N has at least one SDL D, () or () is satisfied under the condition that each MSDL ND in N is transition-live under Mo. () N has no singular MSDL (α) (i.e., (α-) and (α-)). () If N has at least one singular MSDL (α-)((α-), resp.), every semi-MDSL ()((), resp.) NDS = (SDS, TDS, FDS, MoDS with respect to each singular MSDL (α-)((α-), resp.), is transition-live under the MoDS under the condition of "the condition (**)", where the locally structural liveness for this NDS means (1) or (2)((3), resp.) of Lemma 4-4 and "the condition (**)" is defined in Lemma 4-7 of this paper. The relationship between the above results and the liveness problem for N is also shown.

The transmission and processing of multimedia information requires a high-speed communications network infrastructure. This is especially true for the networks between the user's computer and the information highway. An Ethernet LAN is widely used for these networks, but it has limited throughput. Asynchronous Transfer Mode (ATM) LAN technology is a promising approach to overcome this limitation. We have developed a chip set which can be used to connect personal computers (PCs) and workstations (WSs) to a 156-Mbps ATM LAN. The advanced architecture, optimized performance and efficient buffer management enables a sustained more than 100 Mbps transfer speed to be obtained. The chip set is implemented in a 0.8 µm triple metal-layer CMOS process to integrate total 460 K transistors and consumes total 4 W at 5 V.

In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.

This paper describes a 600 mV single-chip MPEG2 video decoder, implemented in a 0.5 µm triple metal CMOS technology, which operates with a 3.3-volt power supply. To achieve low power consumption, a low power dual-port RAM has been developed utilizing a selective bit line precharge scheme to reduce bit line current which is suitable for use in the bit-slice array commonly found in parametric ASIC RAM macro modules. This architecture and a non-DC current sense amp make the RAM's read power consumption one-third of that of a conventional dual-port RAM. Various techniques such as multiple-clock architecture and a system clock independent from a display clock make a system clock frequency as low as possible. The video decoder has a syntax parser, so that it can handle the higher syntactic elements of MPEG2 bit streams without any host processor and decode the Main profile at Main level of MPEG2 bit streams.

In this paper, we propose a new method to measure the 3D object shape without special purpose lighting based upon the Backprojection of Pixel Data.This method need not extract feature points such as edges from images at all and can measure not only the feature points but the whole object surface. It is simply done by project all pixel data back into the object space from each image. Actually, we first assign all pixel data of images into voxels in the object space, and evaluate the variance of assigned data for all voxels. This process is based on the idea that a point on the object surface gives the similar color information or gray level when it is observed from different view points. Then, two kinds of voting are executed as an enhancement process to eliminate the voxels containing the false points. We present experimental results under the circular constraint of camera movement and show the possibility of the proposed method.

This paper proposes an efficient clustering algorithm for region merging. To speed up the search of the best pair of regions which is merged into one region, dissimilarity values of all possible pairs of regions are stored in a heap. Then the best pair can be found as the element of the root node of the binary tree corresponding to the heap. Since only adjacent pairs of regions are possible to be merged in image segmentation, this constraints of neighboring relations are represented by sorted linked lists. Then we can reduce the computation for updating the dissimilarity values and neighboring relations which are influenced by the merging of the best pair. The proposed algorithm is applied to the segmentations of a monochrome image and range images.

We thought that multiple skeletons were inherent in an ordinary three-dimensional object. A thinning method is developed to extract multiple skeletons using 333 templates for boundary deletion based on the hit or miss transformation and 222 templates for checking one voxel thickness. We prepared twelve sets of deleting templates consisting of total 194 templates and 72 one voxel checking templates. One repetitive iteration using one sequential use of the template sets extracts one skeleton. Some of the skeletons thus obtained are identical; however, multiple independent skeletons are extracted by this method. These skeletons fulfill the well-recognized three conditions for a skeleton. We extracted three skeletons from the cube, two from the space shuttle model and four from the L-shaped figure by Tsao and Fu. The digital medial skeleton, which is not otherwise extracted, is extracted by comparing the multiple skeletons with the digital medial-axis-like-figure. One of our skeletons for the cude agreed with the ideal medial axis. The locations of the gravity center of the multiple skeletons are compared with that of the original shape to evaluate how uniform or non-biased skeletons are extracted. For the L-shaped figure, one of our skeletons is found to be most desirable from the medial and uniform points of view.

In this paper we describa a system for Off-line Recognition of Arabic characters and Numerals. This is based on expressing the machine printed Arabic alpha-numerical text in terms of strokes obtained by MCR (Minimum Covering Run) expression. The strokes are rendered meaningful by a labeling process. They are used to detect the baseline and to provide necessary features for recognition. The features selected proved to be effective to the extent that with simple right to left analysis we could achieve interesting results. The recognition is achieved by matching to reference prototypes designed for the 28 Arabic characters and 10 numerals. The recognition rate is 97%.

An analytical framework to study the nonuniformity in geographical distribution of the traffic load in low earth orbit satellite communication systems is presented. The model is then used to evaluate the throughput performance of the system with direct-sequence packet spread-slotted ALOHA multiple-access technique. As the result, it is shown that nonuniformity in traffic makes the characteristics of the system significantly different from the results of uniform traffic case and that the performance of each user varies according to its location. Moreover, the interference reached from users of adjacent satellites is shown to be one of the main factors that limit the performance of system.

This paper presents a new method for solving the structure-from-motion problem for optical flow. The fact that the structure-from-motion problem can be simplified by using the linearization technique is well known. However, it has been pointed out that the linearization technique reduces the accuracy of the computation. In this paper, we overcome this disadvantage by correcting the linearized solution in a statistically optimal way. Computer simulation experiments show that our method yields an unbiased estimator of the motion parameters which almost attains the theoretical bound on accuracy. Our method also enables us to evaluate the reliability of the reconstructed structure in the form of the covariance matrix. Real-image experiments are conducted to demonstrate the effectiveness of our method.

This paper proposes a new method that can robustly recover 3D structure and 3D motion of 3D moving objects from a few multi-views. It recovers 3D feature points by obtaining intersections of back-projection lines which are connected from the camera's optical centers thorough projected feature points on the image planes corresponding to the different cameras. We show that our method needs only six views to suppress false 3D feature points in most cases by discussing the relation between the occurrence probability of false 3D feature points and the number of views. This discussion gives us a criterion to design the optimal multi-camera system for recovering 3D structure and 3D motion of 3D moving objects. An experimental multi-camera system is constructed to confirm the validity of our method. This system can take images from six different views at once and record motion image sequence from each view over a period of a few seconds. It is tested successfully on recovering the 3D structure of Vinus's plaster head and on recovering the 3D structure and 3D motion of a moving hand.

This paper presents some tighter bounds on universal noiseless coding, in particular, the lowerbound tighter than Davisson et al.'s for finite sequence and the upperbound for some typical universal data compression. We find that Davisson et al.'s bound satisfies some optimization in the case of using the Jeffreys prior and also that the derived upperbound in this paper is within O(1/n) from the Clarke and Barron asymptotics in the case of some restricted typical universal data compression defined in the paper.

Petri nets are useful in modeling and analyzing various types of discrete-event systems such as parallel processing systems, distributed systems, and sequential control systems, because Petri nets can easily be used to represent such properties of these systems as concurrency, nondecidability, and causality. Various behavioral analytic problems on Petri nets are reduced to reachability and liveness on them. It is also known that the decidability of liveness is equivalent to that of reachability which is solvable. However, useful necessary and sufficient structural liveness conditions have been given only for extended free-choice (EFC) nets and their subclasses. Moreover recently, a necessary and sufficient structural liveness condition for a useful subclass NKT=(SKT, TKT, FKT, MoKT) (i.e., a Petri net in which each minimal structural deadlock (MSDL) contains at least one real or virtual kindling trap, each locally structural-live MSDL ND=(SD, TD, FD, MoD) is never globally dead even if all key transitions for local liveness of each MSDL are controlled by the net of SKTSD s.t. SKTSD, and there exists no singular MSDL of type (α)) has also been given. In this paper, in order to give one of the bases for a necessary and sufficient "structural" or "initial-marking-based" liveness condition for a general Petri net N, we will, first, directly present a necessary and sufficient local liveness condition for each MSDL with a real deadlock-trap structure in a subclass Ñ (N) using the net structure and initial token distribution and extending basic concepts used in NKT, where Ñ is a general Petri net without live behavioral traps, local liveness means a useful necessary condition for the above final goal, and real deadlock-trap structure means that each MSDL in Ñ contains at least one minimal structural trap. Secondly, a new subclass is shown in which, if the above locally structural liveness condition for each MSDL holds, then the whole-net liveness is also guaranteed. It is also argued that the obtained results are applicable to describing new live behavioral traps and deriving a necessary and sufficient structural liveness condition, which is the final goal in this work, for a general Petri net N.

The performance of decision-feedback equalization combined with maximum-likelihood detection (DFE/ML) using the fixed-delay-tree-search/decision feedback (FDTS/DF) algorithm was estimated analytically in terms of the length of the feedback-filter and the depth of the ML-detector. Performance degradation due to error propagation in the feedback-loop and in the ML-detector was taken into account by using a Markov process analysis. It was quantitatively shown that signal-to-noise-ratio (SNR) performance in high-density magnetic recording channels can be improved by combining an ML-detector with a feedback-filter and that the error propagation in the DFE channel can be reduced by using an ML-detector. Finally, it was found that near-optimum performance with regard to channel SNR and error propagation can be achieved, over the channel density range from 2 to 3, by increasing the sum of the feedback-filter length and the ML-detector depth to six bits.

This paper proposes a protocol verification tool where protocols are described in an extended Petri net and Horn clauses. The extended net model contributes to reduce state space in verification with hierarchical description. The model also includes timed and colored net. Horn clause enables protocol designers to grasp a protocol by the declarative semantics. They can describe non critical but mandatory portion of a protocol like error processing or abortion with Horn clauses. Protocols are verified through simulation. Protocol verification includes two methods, all-in-one and hierarchical methods. By the all-in-one method all description is translated into Prolong clause and simulated exhaustively, whereas by the hierarchical verification, simulation begins with the lowest layer and deduces sufficient conditions that give liveness and safeness of the net model. Then the layer is replaced by a simpler net model that is incorporated into the higher layer. The scheme is applied to an illustrative example of the Alternating Bit protocol to discuss its effectiveness.

Computer circumstance have changed drastically, and larger capacity removable media is indispensable. Magneto-optical disk is promising candidate to satisfy computer user's needs. In this report, future perspective of high density magneto-optical recording technology is investigated.