An integrated pen interface system was developed to allow effective Japanese text entry. It consists of sub-systems for handwriting recognition, contextual post-processing, and enhanced Kana-to-Kanji conversion. The recognition sub-system uses a hybrid algorithm consisting of a pattern matcher and a neural network discriminator. Special care was taken to improve the recognition of non-Kanji and simple Kanji characters frequently used in fast data entry. The post-processor predicts consecutive characters on the basis of bigrams modified by the addition of parts of speech and substitution of macro characters for Kanji characters. A Kana-to Kanji conversion method designed for ease of use with a pen interface has also been integrated into the system. In an experiment in which 2,900 samples of Kanji and non-Kanji characters were obtained from 20 subjects, it was observed that the original recognition accuracy of 83.7% (the result obtained by using the pattern matching recognizer) was improved to 90.7% by adding the neural network discriminator, and that it was further improved to 94.4% by adding the post-processor. The improved recognition accuracy for non-Kanji characters was particularly marked.

In this paper, we propose DSVMA (Data Steal into Voice Multiple Access) scheme for integration of voice and data in wireless information networks. By using speech activity detectors and effective downstream control signals, DSVMA enables data terminals to transmit multi-packet messages when voice terminals are in silent periods. The S-G (throughput versus offered load) performance of the DSVMA system and the blocking probabilities of both the second generation systems and the DSVMA systems are evaluated by the static analysis. A dynamic analysis of a system with finite number of terminals is also presented using an approximate Markov analysis method. Some numerical examples are given in the paper. As a result, it is shown that DSVMA can improve the channel utility efficiency of a circuit-switched TDMA (Time Division Multiple Access) wireless communication system and is directly applicable for second generation wireless information systems.

We apply neural networks to implement a line shape recognition/classification system. The purpose of employing neural networks is to eliminate target-specific algorithms from the system and to simplify the system. The system needs only to be trained by samples. The shapes are captured by the following operations. Lines to be processed are segmented at inflection points. Each segment is extended from both ends of it in a certain percentage. The shape of each extended segment is captured as an approximate curvature. Curvature sequence is normalized by size in order to get a scale-invariant measure. Feeding this normalized curvature date to a neural network leads to position-, rotation-, and scale-invariant line shape recognition. According to our experiments, almost 100% recognition rates are achieved against 5% random modification and 50%-200% scaling. The experimental results show that our method is effective. In addition, since this method captures shape locally, partial lines (caused by overlapping etc.) can also be recognized.

In robot vision system, enormously large computation power is required to perform three-dimensional (3-D) instrumentation and object recognition. However, many kinds of complex and irregular operations are required to make accurate 3-D instrumentation and object recognition in the conventional method for software implementation. In this paper, a VLSI-oriented Model-Based Robot Vision (MBRV) processor is proposed for high-speed and accurate 3-D instrumentation and object recognition. An input image is compared with two-dimensional (2-D) silhouette images which are generated from the 3-D object models by means of perspective projection. Because the MBRV algorithm always gives the candidates for the accurate 3-D instrumentation and object recognition result with simple and regular procedures, it is suitable for the implementation of the VLSI processor. Highly parallel architecture is employed in the VLSI processor to reduce the latency between the image acquisition and the output generation of the 3-D instrumentation and object recognition results. As a result, 3-D instrumentation and object recognition can be performed 10000 times faster than a 28.5 MIPS workstation.

The paper describes the architecture and the simulated performances of a memory-based chip that emulates human cortical processing in early visual tasks, such as texture segregation. The featural elements present in an image are extracted by a convolution block and subsequently processed by the cortical chip, whose neurons, organized into three layers, gain relational descriptions (intelligent processing) through recurrent inhibitory/excitatory interactions between both inter-and intra-layer parallel pathways. The digital implementation of this architecuture directly maps the set of equations determining the status of the cortical network to achieve an optimal exploitation of VLSI technology in neural computation. Neurons are mapped into a memory matrix whose elements are updated through a programmable computational unit that implements synaptic interconnections. By using 0.5 µm-CMOS technology, full cortical image processing can be attained on a single chip (2020 mm2 die) at a rate higher than 70 frames/second, for images of 256256 pixels.

This paper proposes a new fully-digitalized π/4-shift QPSK modulator consisting of a digital pulse shaping filter and a baseband quadrature modulator. By employing a novel digital filter configuration, the required filter memory is reduced to just 6.25% of the conventional one. Moreover, since the proposed baseband modulation scheme does not employ analog mixers or an analog 90 divider, a very accurate, high-stable and compact modulator is realized. It is shown that the proposed scheme achieves excellent low power consumption characteristics and is more suitable for digital LSIC implementation of personal communication terminals than a direct RF modulation scheme and an analog IF modulation scheme.

Artificial Neural Networks (ANN's) that are able to learn exhibit many interesting features making them suitable to be applied in several fields such as pattern recognition, computer vision and so forth. Learning a given input-output mapping can be regarded as a problem of approximating a multivariate function. In this paper we will report a theoretical framework for approximation, based on the well known sequences of functions named approximate identities. In particular, it is proven that such sequences are able to approximate a generally continuous function to any degree of accuracy. On the basis of these theoretical results, it is shown that the proposed approximation scheme maps into a class of networks which can efficiently be implemented with analog MOS VLSI or BJT integrated circuits. To prove the validity of the proposed approach a series of results is reported.

This paper discusses the potential benefits of H0-based ISDN. By providing widespread H0 (384kb/s) call services, much like today's telephone systems, it should be possible to bring multimedia public communication services to the general public. Small distributed switching systems and reuse of existing metallic loops will contribute to its economical construction and rapid expansion into general use. System-on-a-chip technology, expected to appear soon, will make the necessary small switching systems cost-effective. The short loops resulting from the distribution will allow Hl-band (1.5/2.0Mb/s) metallic loops to be used. In terms of function, the distributed switching nodes will permit node-by-node customization, which will make switching systems simple and flexible. The proposed node-by-node customization will allow subscribers in each different node to choose they prefer. H0-based ISDN will provide various type of nodes, supporting various types of subscriber loops, whereas present public networks enforce standardized subscriber loops. Furthermore, when customized subscriber switching systems accommodate star-LAN interfaces as subscriber loops, the public network will be able to provide LAN services in a closed area as part of the public network services. The LAN users will be able to converse with ordinary residential subscribers through H0-calls. This will lead to the integration of LANs and public networks.

In cellular mobile systems, an alternative approach for a Dynamic Channel Assignment problem is presented. It adaptively assigns the channels considering the cochannel interference level. The Dynamic Channel Assignment problem is modeled on the different cellular system from the conventional one. In this paper, we formulate the rearrangement problem in the Dynamic Channel Assignment and propose a novel strategy for the problem. The proposed algorithm is based on an artificial neural network as a specific dynamical system, and is successfully applied to the cellular system models. The computer simulation results show that the algorithm utilized for the rearrangement is an effective strategy to improve the traffic characteristics.

This paper proposes high-performance multiprocessor implementation for real-time one-dimensional (1-D) statespace digital filters (SSDFs). The block-state realization of SSDFs (BSRDF) is suitable for their high speed realization and gives the characteristics of high accuracy. Previously we proposed a VLSI-oriented highly parallel architecture for BSRDF. For the purpose of speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends only on word length, is applied to this architecture. It is implemented as a 2-D SIMD processor array, and the processor consists of n homogeneous processing elements (PEs), n being filter order. The high sampling rate of one or more hundred MHz becomes possible for high filter order. Moreover, the number of I/O data per processor can be a small fixed value for any filter order, and the number of gates can also be smaller than that in the case of using multiplier. Consequently, this proposed system can be implemented easily even in the present VLSI environment.

Pitch frequency is a basic characteristic of human voice, and pitch extraction is one of the most important studies for speech recognition. This paper describes a simple but effective technique to obtain correct pitch frequency from candidates (pitch candidates) extracted by the short-range autocorrelation function. The correction is performed by a neural network in consideration of the time coutinuation that is realized by referring to pitch candidates at previous frames. Since the neural network is trained by the back-propagation algorithm with training data, it adapts to any speaker and obtains good correction without sensitive adjustment and tuning. The pitch extraction was performed for 3 male and 3 female announcers, and the proposed method improves the percentage of correct pitch from 58.65% to 89.19%.

A pseudoinverse rule, one of major rule to determine a weight matrix for associative memory, has large capacity comparing with other determining rules. However, it is wellknown that the rule has small domains of attraction of memory vectors on account of many spurious states. In this paper, we try to improve the problem by means of subtracting a constant from all diagonal elements of a weight matrix. By this method, many spurious states disappear and eigenvectors with negative eigenvalues are introduced for the orthocomplement of the subspace spanned by memory vectors. This method can be applied to two types of networks: binary network and analog network. Some computer simulations are performed for both two models. The results of the simulations show our improvement is effective to extend error correcting ability for both networks.

An approach to estimate the information of moving objects is described in terms of their kinetic and static properties such as 2D velocity, acceleration, position, and the size of each object for the features of motion snd shape. To obtain the information of motion/shape of multiple objects, an advanced contour matching scheme is developed, which includes the synthesis of edge images and the analysis of object shape with a high matching confidence as well as a low computation cost. The scheme is composed of three algorithms: a motion estimation by an iterative triple cross-correlation, an image synthesis by shifting and masking the object, and a shape analysis for determining the object size. Implementing fuzzy membership functions to the object shape, the scheme gets improved in accuracy of capturing motion and shape of multiple moving objects. Experimental result shows that the proposed method is valid for several walking men in real scene.

In an earlier paper, we have shown that each section of the L-section minimal trellis diagram for a linear block code consists of parallel and structurally identical (except branch labels) subgraphs without cross connections. These parallel subgraphs are called parallel components of the section. In this paper, it is shown that if the sets of path label sequences of two parallel components have a common sequence, then the parallel components have the same branch labels, and the number of parallel components with the same branch labels in each section and the detail structure of each parallel component up to its branch labels are analyzed and expressed in terms of the dimensions of specific linear codes related to the given code. As an example, the 2i-section minimal trellis diagram for a Reed-Muller code is analyzed. Complexity measures of soft-decision maximum likelihood decoding for binary linear block codes are also discussed.

This paper describes a novel technique to realize high performance digital sequential circuits by using Hopfield neural networks. For an example of applications of neural networks to digital circuits, a novel gate circuit, full adder circuit and latch circuit using neural networks, which have the global convergence property, are proposed. Here, global convergence means that the energy function is monotonically decreasing and each circulit always operates correctly independently of the initial values. Finally the several digital sequential circuits such as shift register and asynchronous binary counter are designed.

This paper discusses a common channel signaling system in which multiple micro-switching systems can converse as though configured like a conventional centralized switching system. A micro-switching system is a switching system whose main functions are integrated on a chip, like a microprocessor. Progress in MOS technology will soon make micro-switching systems possible, and their small scale and economy will allow subscriber switching systems to be distributed closer to subscribers. This will allow shorter subscriber loops, so subscriber networks will be able to reuse existing metallic lines as H1 (1.544/2.048Mb/s)-class subscriber loops. Economical micro-switching systems and reuse of existing network resources will contribute to the establishment H0 (384kb/s)-ISDN, so that every subscriber will be able to enjoy multimedia communications through HO-calls as simply as using present telephones. Four alternative signaling network architectures are examined, classified by arrangement of their signaling transfer junctions and signaling links, and a new signaling system featuring cell-based transfer functions is proposed. This is suitable for a distributed micro-switching-system network in order to minimize the figures of merit, which collectively estimate network cost and signaling delay.

A very-high-speed ten-neuron analog neural network LSI chip is fabricated for the first time using super self-aligned Si bipolar process technology. The LSI consists of ten neurons and 100 electrically modifiable synaptic weights. The neural network nonlinear mapping function to solve the four-bit parity problem is successfully demonstrated at 150 mega-patterns/sec. The operation speed of this neural network is, to the best of the authors, knowledge, the fastest yet reported.

Distributed algorithms that entail successive rounds of message exchange are called decentralized consensus protocols. Several consensus protocols use a finite projective plane as a communication structure and require 4nn messages in two rounds, where n is the number of nodes. This paper presents an efficient communication structure that uses a finite projective plane with a duality of indices. The communication structure requires 2nn messages in two rounds, and can therefore halve the number of messages. It is shown that a finite projective plane with a duality can be constructed from a difference set, and that the presented communication structure has two kinds of symmetry.

This paper presents an adaptive MLSE (Maximum Likelihood Sequence Estimator) suitable for TDMA cellular systems. The proposed MLSE has two special features such as handling wide dynamic range signals without analogue gain controls and fast channel tracking capability. In order to handle wide dynamic range signals without conventional AGCs (Automatic Gain Controller), the proposed MLSE uses envelope components of received signals obtained from a non-linear log-amplifier module which has wide log-linear gain characteristics. By using digital signal processing technique, the log-converted envelope components are normalized and converted to linear values which conventional adaptive MLSEs can handle. As a channel tracking algorithm of the channel estimator, the proposed MLSE adopts a QT-LMS (Quick-Tracking Least Mean Square) algorithm, which is obtained by modifying LMS algorithm to enable a faster tracking capability. The algorithm has a fast tracking capability with low complexity and is suitable for implementation in a fixed-point digital signal processor. The performances of the MLSE have been evaluated through experiments in TDMA cellular environments with π/4-shifted QPSK, 24.3k symbol/sec. It is shown that, under conditions of 65dB amplitude variations and 80Hz Doppler frequency, the MLSE successfully achieves less than 3% B.E.R., which is required for digital cellular systems.

This paper proposes a new strategy for reducing contention for a critical section in a multiprocessor system and shows that the strategy can improve CPU utilization by several percent. Using simulation and queueing theory, it also discusses when the strategy is superior to conventional ones.