It has become more important to shorten development periods of high performance computer systems and their LSIs. During debugging of computer prototypes, logic designers request very frequent LSI refabrication to change logic circuits and to add some functions in spite of their extensive logic simulation by several GFLOPS supercomputers. To meet these demands, an automated on-chip direct wiring modification system has been developed, which enables wire-cut and via-digging by a precise focused ion beam machine, and via-filling and jumper-writing by a laser CVD machine, directly on pre-redesign (original) chips. This modification system was applied to LSI reworks during the development of Hitachi large scale computers M-880 and S-3800, and contributed to shorten system debugging period by four to six months.

A new method for simulation of etching and deposition processes has been developed. This method is based on fundamental morphological operations derived from image and signal processing. As the material surface during simulation moves in time, the geometry either increases or decreases. If the simulation geometry is considered as a two-valued image (material or vacuum), etching and deposition processes can be simulated by means of the erosion and dilation operation. Together with a cellular material representation this method allows an accurate and stable simulation of three-dimensional arbitrary structures. Simulation results for several etching and deposition problems demonstrate accuracy and generality of our method.

This paper presents a view on coming photonic network in which machines are potential customer to the network. The network will be providing unlimited number of virtual free spaces in which point to point and broadcasting modes of information interchanges are taking place simultaneously. It is also pointed out that the Asynchronous Transfer Mode (ATM) should be evolved to support this type of network by using true photonic switching technology.

From the viewpoint of customer's satisfaction, precise information and rapid action are very important when complaints about call connection failures or service quality deterioration come from customers. It is indispensable to the propose that operators are supported by an operation system which stores and processes each customer's information, their complaint's histories, network failure status and call connection detail data. This paper shows functions and Human Machine Interface (HMI) of Customer Complaint Handling System (CCHS). This system can handle a customer's complaint by an electric ticket and necessary information is automatically collected and shown on the ticket.

Directional dry etching of Tantalum is described X-ray lithography absorber patterns. Experiments are carried out using both reactive ion etching in CBrF3-based plasma and electron-cyclotron-resonance ion-stream etching in Cl2-based plasma. Ta absorber patterns with perpendicular sidewalls cannot be obtained by RIE when only CBrF3 gas is used as the etchant. While adding CH4 to CBrF3 effectively improves the undercutting of Ta patterns, it deteriorates etching stability because of the intensive deposition effect of CH4 fractions. By adding an Ar/CH4 mixture gas to CBrF3, it is possible to use RIE to fabricate 0.2-µm Ta absorber patterns with perpendicular sidewalls. ECR ion-stream etching is investigated to obtain high etching selectivity between Ta and SiO2 (etching mask)/SiN (membrane). Adding O2 to the Cl2 etchant improves undercutting without remarkably decreasing etching selectivity. Furthermore, an ECR ion-stream etching method is developed to stably etch Ta absorber patterns finer than 0.2µm. This is successfully applied to X-ray lithography mask fabrication for LSI test devices.

As a general basis for constructing a cooperative and flexible dialogue system, we are interested in modelling the inference process of an agent who participates in a dialogue. For this purpose, it is natural and powerful to model it in his general cognitive framework for problem solving. This paper presents such a framework. In this framework, we represent agent's mental states in the form called Mental World Structure, which consists of multiple mental worlds. Each mental world is a set of mental propositions and corresponds to one modal context, that is, a specific point of view. Modalities in an agent's mental states are represented by path expressions, which are first class citizens of the system and can be composed each other to make up composite modalities. With Mental World Structure, we can handle modalities more flexibly than ordinary modal logics, situation theory and other representation systems. We incorporate smoothly into the structure three basic inference procedures, that is, deduction, abduction and truth maintenance. Precise definitions of the structure and the inference procedures are given. Furthermore, we explain as examples, several cooperative dialogues in our framework.

The paper studies a high-ranking node in a broadband integrated services digital network(B-ISDN). The input traffic is classified into two types: real-time and non-real-time. For each type of input traffic, we assume that the message arrival process is a batch Poisson process and that the message size is arbitrarily distributed so as to describe services from narrowband to wideband. We model the high-ranking node by a queueing system with multiple synchronous servers and two separate finite buffers, one for each type of traffic. We derive performance measures exactly by using a two-dimensional imbedded discrete-time Markov chain analysis, within which the transition probabilities are obtained via an application of the residue theorem in complex variables. The performance measures include the blocking probability, delay, and throughput.

An analog approach alternative to the Hopfield method is presented for solving constrained combinatorial optimization problems. In this new method, a saddle point of a Lagrangian function is searched using a constrained dynamical system with the aid of an appropriate transformation of variables. This method always gives feasible solutions in contrast to the Hopfield scheme which often outputs infeasible solutions. The convergence of the method is proved theoretically and some effective schemes are recommended for eliminating some variables for the case we resort to numerical simulation. An analog electronic circuit is devised which implements this method. This circuit requires fewer wirings than the Hopfield networks. Furthermore this circuit dissipates little electrical power owing to subthreshold operation of MOS transistors. An annealing process, if desired, can be performed easily by gradual increase in resistance of linear resistors in contrast to the Hopfield circuit which requires the variation in the gain of amplifiers. The objective function called an energy is ensured theoretically to decrease throughout the annealing process.

In this paper, we clarify fundamental properties of conventional back-propagation neural networks to learn chaotic dynamical systems by some numerical experiments. We train three-layers networks using back-propagation algorithm with the data from two examples of two-dimensional discrete dynamical systems. We qualitatively evaluate the trained networks with two methods analysing geometrical mapping structure and reconstruction of an attractor by the recurrent feedback of the networks. We also quantitatively evaluate the trained networks with calculation of the Lyapunov exponents that represent the dynamics of the recurrent networks is chaotic or periodic. In many cases, the trained networks show high ability of extracting mapping structures of original two-dimensional dynamical systems. We confirm that the Lyapunov exponents of the trained networks correspond to whether the reconstructed attractors by the recurrent networks are chaotic or periodic.

As promising copy networks of very large multicast switching networks for Broadband ISDN, multi-stage Recursive Copy Networks (RCN) have been proposed recently. In the multicast switch structure, the RCN precedes a point-to-point switch. At an RCN, all the copies of a master cell are generated recursively, i.e., a few copies of the master cell are made initially, and by considering each of these copies to be master cells, more copies are made which, in turn, are again considered to be master cells to make still more copies, the process thus progressing recursively till all the required copies are made. By this principle of recursive generation of copies, the number of copies that can be generated is independent of the hardware size of the RCN. A limitation of RCNs is that buffer sizes at all stages except the first stage have to be large so as to keep the cell loss due to buffer overflow within desired limits. This paper inspects a flow control scheme by which the probability of buffer overflow can be kept low, even though the buffer sizes at later stages are not large. Under this flow control procedure, a cell is not transmitted from a stage to the succeeding stage, if the occupancy level of the buffer of the succeeding stage exceeds a threshold. We study by simulation the performance aspects of such a flow control scheme in RCNs under cut-through switching scheme and under store-and-forward switching scheme. At high load intensities, the overflow probability can be reduced by an order of magnitude in 2-stage RCNs and by two orders of magnitude in 3-stage RCNs. To restrict the overflow probability within a given limit, the required buffer size is less under flow control than under no flow control. The implementation of the flow control is simple and the control overhead is small, thereby making the scheme attractive for implementation in high speed switching environments. Further, the proposed flow control scheme does not disturb the cell sequence.

In this paper, we analyze the throughput of the Stop-and-wait and Go-back-N ARQ schemes over an unreliable channel modeled by the two-state Markov process. Generally, in these states, block error probabilities are different. From analytical results and numerical examples, we show that the throughput of the Stop-and-wait ARQ scheme only depends on overall average error probability, while that of the Go-back-N ARQ scheme depends on the characteristic of the Markov process.

A transmission data format for high-speed optical parallel interconnections is proposed and a 4-channel transmitter and receiver link module operating at up to 1.2 Gb/s per channel is demonstrated. The data format features "Group Multiplexing and Coding." In this scheme, input several tens channels are multiplexed and coded in group into reduced channels, resulting in burst-mode compatible, skew-free transmission, and low power-consumption of a link module. Experiments with fabricated modules comfirm that our data coding in multichannel optical transmission is promising for use in high-speed interconnections in information and switching systems.

The crosstalk characteristics of a long-wavelength monolithically integrated photoreceiver array are analyzed. The device consists of an array of transimpedance photoreceivers fabricated on a semi-insulating InP substrate. The distance between the photodetectors is large enough to suppress the photonic crosstalk. Therefore, the crosstalk of the device is mainly due to signal propagation from the channels through the power line shared by each channel on the chip. This crosstalk is inevitable to the photoreceiver arrays which employ common power lines. The magnitude of the crosstalk largely depends on the impedance of the power-supply circuit outside the chip. The crosstalk spectrum often has a peak and recess structure. The crosstalk peak at the edge of the operating band-width is due to the resonance characteristic of the transimpedance amplifier. The other peak and recess structures on the spectrum are due to the resonance phenomena of on-chip and off-chip capacitors and inductance on the power-supply line outside the chip. This crosstalk can be reduced by using on-chip bypass capacitance and dumping resistance. However, the resonance due to the capacitance and inductance on the power-supply circuit outside the chip can't be controlled by the on-chip components. Therefore, an optimized design for the power supply circuit outside the chip is also indispensable for suppressing crosstalk.

This paper presents an improved current-mode circuit for implementation of a chaotic neuron model. The proposed circuit uses a switched-current integrator and a nonlinear output function circuit, which is based on an operational transconductance amplifier, as building blocks. Is is shown by SPICE simulations and experiments using discrete elements that the proposed circuit well replicates the behavior of the chaotic neuron model.

Ultrahigh speed and low crosstalk four-channel receiver optoelectronic integrated circuit (OEIC) arrays comprising GaInAs pin PDs and A1InAs/GaInAs HEMTs have been successfully fabricated on an InP substrate. These arrays were designed to have good crosstalk characteristics which are the most critical issue in array devices. The resistive-load OEIC arrays exhibited high speed operation up to 5 Gb/s and low crosstalk of less than -38 dB between whole adjacent channels over entire frequency range below 4.0 GHz. The average sensitivity of resistive-load OEIC arrays was -18.5 dBm at 3 Gb/s for a bit-error-rate of 10-9 over four channels. Good uniformity of device characteristics was obtained over 2-inch InP wafer. These results suggest that receiver OEIC arrays are quite promising for the application to high-speed multi-channel optical interconnections.

This paper describes the concepts and methodologies of the INTELLITUTOR system which is an integrated intelligent programming environment for learning programming. INTELLITUTOR attempts to work as a human programming tutor to guide a user, i.e., a student, in writing a computer program, to detect logical errors within it, and to make advices not only for fixing them but also for letting him notice his misunderstandings. The system consists of three major modules, i.e., GUIDE, ALPUS and TUTOR. GUIDE is a guided editor for easy coding, ALPUS is an algorithm-based program understander, and TUTOR is an embedded-intelligent tutoring system for programming education. The ALPUS system can infer user's intentions from buggy codes in addition to detecting logical errors by means of knowledge-based reasoning. ALPUS uses four kinds of programming knowledge: 1) knowledge on algorithms, 2) Knowledge on programming techniques, 3) Knowledge on a programming language, and 4) Knowledge on logical errors. These knowledge are organized in a hierarchical procedure graph (HPG) as a multi-use knowledge base. The knowledge on logical errors was obtained by means of cognitive experiments. The student model is built by means of the results of ALPUS and interactions between a student and the system. Teaching is done based on the student model. Because the ITS subsystem, i.e., TUTOR, is embedded within the intelligent programming environment interactions for creating the student model could be minimized. Although the current system deals with the PASCAL language, most of the knowledge is applicable to those of procedure-oriented programming languages. The INTELLITUTOR system was implemented in the frame-based knowledge engineering environment ZERO and working on a UNIX workstation for system evaluation.

In this paper, we investigate the knowledge complexity of interactive proof systems and show that (1) under the blackbox simulation, if a language L has a bounded move public coin interactive proof system with polynomially bounded knowledge complexity in the hint sense, then the language L itself has a one move interactive proof system; and (2) under the blackbox simulation, if a language L has a three move private coin interactive proof system with polynomially bounded knowledge complexity in the hint sense, then the language L itself has a one move interactive proof system. These results imply that as long as the blackbox simulation is concerned, any language L AM＼MA is not allowed to have a bounded move public coin (or three move private coin) interactive proof system with polynomially bounded knowledge complexity in the hint sense unless AM = AM. In addition, we present a definite distinction between knowledge complexity in the hint sense and in the strict oracle sense, i.e., any language in AM (resp. IP) has a two (resp. unbounded) move public coin interactive proof system with polynomially bounded knowledge complexity in the strict oracle sense.

In this paper an identity-based non-interactive key sharing scheme (IDNIKS) is proposed in order to realize the original concept of identity-based cryptosystem, of which secure realization scheme has not been proposed. First the necessary conditions for secure realization of IDNIKS are considered from two different poinrts of view: (i) the possibility to share a common-key non-interactively and (ii) the security for entity's conspiracy. Then a new non-interactive key sharing scheme is proposed, of which security depends on the difficulty of factoring. The most important contribution is to have succeeded in obtaining any entity's secret information as an exponent of the obtainer's identity information. The security of IDNIKS for entity's conspiracy is also considered in details.

In a probabilistic graph (network), source-to-all-terminal (SAT) reliability may be defined as the probability that there exists at least one path consisting only of successful arcs from source vertex s to every other vertex. In this paper, we define an optimal SAT reliability formula to be the one with minimal number of literals or operators. At first, this paper describes an arc-reductions (open- or short-circuiting) method for obtaining a factored formula of directed graph. Next, we discuss a simple strategy to get an optimal formula being a product of the reliability formulas of vertex-section graphs, each of which contains a distinct strongly connected component of the given graph. This method reduces the computing cost and data processing effort required tu generate the optimal factored formula, which contains no identical product terms.

In this paper, we study the knowledge tightness of zero-knowledge proofs. To this end, we present a new measure for the knowledge tightness of zero-knowledge proofs and show that if a language L has a bounded round zero-knowledge proof with knowledge tightness t(|x|) 2 - |x|-c for some c 0, then L BPP and that any language L AM has a bounded round zero-knowledge proof with knowledge tightness t(|x|) 2-2-O(|x|) under the assumption that collision intractable hash functions exist. This implies that in the case of a bounded round zero-knowledge proof for a language L BPP, the optimal knowledge tightness is "2" unless AM = BPP. In addition, we show that any language L IP has an unbounded round zero-knowledge proof with knowledge tightness t(|x|) 1.5 under the assumption that nonuniformly secure probabilistic encryptions exist.