This paper demonstrates that a 360° radio-frequency phase detector consisting of a combination of symmetrical mixers and 45° phase shifters with tunable devices can achieve a low phase-detection error over a wide frequency range. It is shown that the phase detection error does not depend on the voltage gain of the 45° phase shifter. This allows the usage of tunable devices as 45° phase shifters for a wide frequency range with low phase-detection errors. The fabricated phase detector having tunable low-pass filters as the tunable device demonstrates phase detection errors lower than 2.0° rms in the frequency range from 3.0 GHz to 10.5 GHz.

This study proposes a multiple-output differential-input operational transconductance amplifier-C (MODI OTA-C) filter with an impedance scaler to detect cardiac activity. A ladder-type fifth-orderButterworth low-pass filter with a large time constant and low noise is implemented to reduce coefficient sensitivity and address signal distortion. Moreover, linearized MODI OTA structures with reduced transconductance and impedance scaler circuits for noise reduction are used to achieve a wide dynamic range (DR). The OTA-based circuit is operated in the subthreshold region at a supply voltage of 1 V to reduce the power consumption of the wearable device in long-term use. Experimental results of the filter with a bandwidth of 250 Hz reveal that DR is 57.6 dB, and the harmonic distortion components are below -59 dB. The power consumption of the filter, which is fabricated through a TSMC 0.18 µm CMOS process, is lower than 390 nW, and the active area is 0.135 mm2.

Noise and area consumption has been a trade-off in circuit design. Especially for switched-capacitor filters (SCF), kT/C noise gives a limitation to the minimum value of unit capacitance. In case of SCFs with a large capacitance spread, this limitation will result in a large area consumption due to large capacitors. This paper introduces a technique to reduce capacitance spread using charge scaling. It will be shown that this technique can reduce total capacitance of SCFs without deteriorating their noise performances. A design method to reduce the output noise of SC low-pass filters (LPF) based on the combination of cut-set scaling, charge scaling and adaptive configuration is proposed. The proposed technique can reduce the output noise voltage by 30% for small input signals.

A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.

The simple repetitive control system proposed by Yamada et al. is a type of servomechanism for periodic reference inputs. This system follows a periodic reference input with a small steady-state error, even if there is periodic disturbance or uncertainty in the plant. In addition, simple repetitive control systems ensure that transfer functions from the periodic reference input to the output and from the disturbance to the output have finite numbers of poles. Yamada et al. clarified the parameterization of all stabilizing simple repetitive controllers. Recently, Yamada et al. proposed the parameterization of all stabilizing two-degrees-of-freedom (TDOF) simple repetitive controllers that can specify the input-output characteristic and the disturbance attenuation characteristic separately. However, when using the method of Yamada et al., it is complex to specify the low-pass filter in the internal model for the periodic reference input that specifies the frequency characteristics. This paper extends the results of Yamada et al. and proposes the parameterization of all stabilizing TDOF simple repetitive controllers with specified frequency characteristics in which the low-pass filter can be specified beforehand.

A compact and wide stopband low-pass filter (LPF) which consists of a hairpin structural resonator, a chip-capacitor, and inductor lines is proposed in this paper. With the capacitor loaded, the hairpin structure realized three transmission zeros in the stopband. The LPF with one hairpin unit was designed using the conventional prototype design procedure in the passband. To further improve the stopband characteristics, the LPF with three hairpin units was studied and designed with the same manner as in a one unit LPF. The finally designed three-hairpin LPF showed mostly 60 dB rejection characteristics in the conjunction with defected ground condition for avoiding the spurious response at the stopband. The measurement results agreed well with simulated ones.

In this paper, a highly linear and low noise CMOS active RF tracking filter for a digital TV tuner is presented. The Gm cell of the Gm-C filter is based on a dynamic source degenerated differential pair with an optimized transistor size ratio, thereby providing good linearity and high-frequency operation. The proposed RF tracking filter architecture includes two complementary parallel paths, which provide harmonic rejection in the low band and unwanted signal rejection in the high band. The fabricated tracking filter based on a 0.13 µm CMOS process shows a 48860 MHz tracking range with 30–32 dB 3rd order harmonic rejection, a minimum input referred noise density of 2.4 nV/, and a maximum IIP3 of 0 dBm at 3 dB gain while drawing 39 mA from a 1.2-V supply. The total chip area is 1 mm0.9 mm.

Source-follower-based (SFB) continuous-time low-pass filters (LPF) have the advantages of low power and high linearity over other filter topologies. The second-order SFB filter cells, which are key building blocks for high-order SFB filters, are often realized by composite source follower with positive feedback. For a single branch 2nd-order SFB cell, the linearity drops severely at high frequencies in the pass band because its slew-rate is restricted by the Q factor and the pole frequency. The folded 2nd-order SFB cell provides higher linearity because it has two DC branches, and hence has another freedom to increase the slew rate. However, because of the positive feedback, the folded and unfolded 2nd-order SFB cells, especially those with high Q factors, tend to be unstable and act as relaxation oscillators under given circuit parameters. In order to obtain higher Q factor, a new topology for the 2nd-order SFB cell without positive feedback is proposed in this paper, which is unconditionally stable and can provide high linearity. Based on the folded 2nd-order SFB cell and the proposed high-Q SFB cell, a 264 MHz sixth-order LPF with 3 stages for ultra wideband (UWB) applications is designed in 0.18 µm CMOS technology. Simulation results show that the LPF achieves an IIP3 of above 12.5 dBm in the whole pass band. The LPF consumes only 4.1 mA from a 1.8 V power supply, and has a layout area of 200 µm 150 µm.

A 2 GHz gain equalizer for analog signal transmission using a novel gain compensation method is described in this paper. This method is based on feedforward compensation by a low-pass filter, which improves the gain-equalizing performance by subtracting low-pass filtered signals from the directly passed signal at the end of a transmission line. The advantage of the proposed method over the conventional one is that the gain is equalized with a smaller THD at higher frequencies by using a low-pass instead of a high-pass filter. In this circuit, the peak gain is adjustable from 0 to 2.4 dB and the frequency of the peak gain can be controlled up to 2 GHz by varying the value of an external capacitor. Also this circuit achieves THD with 5 dB better than the conventional circuits.

In this paper, a microstrip lowpass filter using hairpin structure and Chip-Capacitor is proposed. Firstly, the LPF with one hairpin element is briefly designed and optimized with LC prototype structure using circuit simulator. With the capacitor loaded the proposed LPF illustrates the sharp attenuation performance near the cut-off frequency and the wideband rejection characteristics. Then, in order to improve the stopband attenuation the three-hairpin LPF is studied. By optimazing its design the attenuation is improved by 32 dB.

A rotary inverted pendulum is stabilized by a single first order dynamic output feedback system. Numerical simulations and experimental results show that the proposed control law has low-pass filter property as well as it can successfully replace the velocity measurements for LQR control law.

In this paper, a new formulation of equal-length three-section open stubs having two zeros located on the unit circle and one zero at z=-1 (θ=π) in the Z-plane is presented. In particular, new filter configurations consisting of equal-length two-section open stubs, cascade lines, open stubs, and three-section open stubs are employed to emulate the discrete-time filters. To examine the validity of our formulation, we realized two discrete-time Chebyshev type II low-pass filters in the form of microstrip lines. The frequency responses of these two filters are measured to validate this new formulation.

A multi-path structure is proposed for reduction in effect of digital substrate noise which degrades analog circuit performance. As an example low-pass filters are implemented in a 0.18-µm CMOS process. 11-dBm reduction in digital substrate noise is achieved as compared with a conventional structure.

In this letter, the fabrication of a compact and high performance semi-lumped coplanar waveguide low-pass filter (CPW-LPF) on high resistivity silicon (HRS) substrate at millimeter wave is proposed. The design procedure and the equivalent circuit of the proposed semi-lumped CPW-LPF is discussed. The filter structure of is very simple but its performances is fairly good. This designed filter at cutoff frequency fc of 31 GHz has very good measured characteristics including the low insertion loss, sharp rejection and low group delay, due to the reduced substrate loss of HRS. Experimental results of the fabricated filter show a good agreement with the predicted results.

A design method for an ultra-wideband bandpass filter (BPF) with four coupled lines has been developed. For demonstration purposes, 50 Ω-matched self-complementary antennas integrated with the ultra-wideband, differential-mode BPF with four coupled lines, a notch filter, and a low-pass filter (LPF) were prepared and tested. An optimized structure for a single-stage, broadside-coupled and edge-coupled four-lines BPF was shown to exhibit up to 170% fractional bandwidth and an impedance transformation ratio of 1.2 with little bandwidth reduction, both analytically and experimentally. Using the optimized structure, 6-stage BPFs were designed to transform the self-complementary antenna's constant input impedance (60πεe- 1/2(Ω)) to 50 Ω without degrading bandwidth. In addition, two types of filter variations--a LPF-embedded BPF and a notch filter-embedded BPF--were designed and fabricated. The measured insertion loss of both filter systems was less than 2.6 dB over the ultra-wideband (UWB) band from 3.1 GHz to 10.6 GHz. The filter systems were embedded in the wideband self-complementary antennas to reject unnecessary radiation over the next pass band and 5-GHz wireless LAN band.

The Evolutionary Electronics refers to the design method of electronic circuits with the help of Evolutionary Algorithms. Over the years huge experience has been accumulated and tremendous results have been achieved in this field. Two obvious tendencies are prevailing in the area over designers to improve the performance of Evolutionary Algorithms. First of all, as with any solution-search-algorithm, the designers try to reduce the potential solution space in order to reach the optimum solution faster, putting some constrains onto search algorithm as well as onto potential solutions. At the same time, the second tendency of unconstraining the Evolutionary Algorithms in its search gives unpredictable breakthroughs in results. Enabling the evolution to optimize with more experimental parameters devoted to drive the evolution and adjusted previously manually, is one of an example where such kind of unconstraining takes place. The evolution with the maximum freedom of search can be addressed as unconstrained evolution. The unconstrained evolution has already been applied in the past towards the design of digital circuits, and extraordinary results have been obtained, including generation of circuits with smaller number of electronic components. Recently, the similar method has been introduced by authors of this paper towards the design of analogue circuits. The new algorithm has produced promising results in terms of quality of the circuits evolved and evolutionary resources required. It differed from constrained method by its simplicity and represented one of the first attempts to apply Evolutionary Strategy towards the analogue circuit design. In this paper both conventional constrained evolution and newly developed unconstrained evolution in analogue domain are compared in detail on the example of "LC" low-pass filter design. The unconstrained evolution demonstrates the superior behaviour over the constrained one and exceeds by quality of results the best filter evolved previously by 240%. The experimental results are presented along with detailed analysis. Also, the obtained results are compared in details with low-pass filters designed previously.

We propose a third-order low-pass notch filter realized by a single operational amplifier and a minimum number of equal-valued capacitors. As a design example we realize a Chebyshev filter with a ripple of 0.5 dB and it is shown that the experiment result is very good.