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Naoya TATE Tadashi KAWAZOE Shunsuke NAKASHIMA Wataru NOMURA Motoichi OHTSU
In order to realize high-yield speckle modulation, we developed a novel spatial light modulator using zinc oxide single crystal doped with nitrogen ions. The distribution of dopants was optimized to induce characteristic optical functions by applying an annealing method developed by us. The device is driven by a current in the in-plane direction, which induces magnetic fields. These fields strongly interact with the doped material, and the spatial distribution of the refractive index is correspondingly modulated via external control. Using this device, we experimentally demonstrated speckle modulation, and we discuss the quantitative superiority of our approach.
Hiroshi GOTO Hiroaki TAO Shinya MORITA Yasuyuki TAKANASHI Aya HINO Tomoya KISHI Mototaka OCHI Kazushi HAYASHI Toshihiro KUGIMIYA
We have investigated the microwave-detected photoconductivity responses from the amorphous In--Ga--Zn--O (a-IGZO) thin films. The time constant extracted by the slope of the slow part of the reflectivity signals are correlated with TFT performances. We have evaluated the influences of the sputtering conditions on the quality of a-IGZO thin film, as well as the influences of gate insulation films and annealing conditions, by comparing the TFT characteristics with the microwave photoconductivity decay ($mu$-PCD). It is concluded that the $mu$-PCD is a promising method for in-line process monitoring for the IGZO-TFTs fabrication.
Satoshi YASUNO Takashi KITA Shinya MORITA Aya HINO Kazushi HAYASHI Toshihiro KUGIMIYA Shingo SUMIE
Microwave photoconductivity decay (µ-PCD) method was applied to evaluate the effects of chemical composition and Ar+ plasma induced damage on the bulk and the surface states in amorphous In-Ga-Zn-O (a-IGZO) films. It was found that the peak reflectivity signal in the photoconductivity response increased with decreasing the Ga content, and had a strong correlation with the a-IGZO transistor performances. In addition, the peak reflectivity signals obtained after various Ar+ plasma treatment duration were well correlated with the transistor characteristics. With Ar+ plasma treatment, the peak reflectivity signal decreased in accordance with degradation of transistor characteristics. The µ-PCD method was found to be a very useful tool not only to evaluate the bulk and the surface states, but also to predict the performance of a-IGZO transistors subjected to various plasma processes in the production.
Shinya MORITA Satoshi YASUNO Aya MIKI Toshihiro KUGIMIYA
We have studied effects of additive elements into the channel layers of amorphous IGZO TFTs on threshold voltage shift issues under light illumination stress condition. By addition of Hf or Si element, the Vth shift under light illumination and negative bias-temperature stress and illumination stress conditions was drastically suppressed while the switching operation of TFTs using IGZO with Mn or Cu was not observed. It was found that the addition of Si or Hf element into the IGZO channel layer leads to reducing the hole trap sites formed at or near the gate insulator/IGZO channel interface.
Tuan Thanh TA Suguru KAMEDA Tadashi TAKAGI Kazuo TSUBOUCHI
In this paper, a fully integrated 5 GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18 µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1 GHz to 6.1 GHz (relative value of 17.9%) and phase noise of lower than -110.8 dBc/Hz at 1 MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182 dBc/Hz.
Seok-Ju YUN Dae-Young YOON Sang-Gug LEE
A novel CMOS LC quadrature oscillator (QO) which adopts complementary-coupling circuitry has been proposed. The performance improvement in I/Q phase error and phase noise of the proposed QO, is explained in comparison with conventional QOs. The proposed QO is implemented in 0.18 µm CMOS technology along with conventional QOs. The measurement result of the proposed QO shows -133.5 dBc/Hz of phase noise at 1 MHz offset and 0.6 I/Q phase difference, while oscillating at 1.77 GHz. The proposed QO shows more than 6.5 dB phase noise improvement compared to that of the conventional QOs over the offset frequency range of 10 K-1 MHz, while dissipating 4 mA from 1.4 V supply.
Manabu ITO Masato KON Chihiro MIYAZAKI Noriaki IKEDA Mamoru ISHIZAKI Yoshiko UGAJIN Norimasa SEKINE
We demonstrate a novel display structure for color electronic paper for the first time. Fully transparent amorphous oxide TFT array is directly deposited onto color filter array and combined with E Ink Imaging Film. Taking advantage of the transparent property of the oxide TFT, the color filter and TFT array are positioned at the viewing side of the display. This novel "Front Drive" display structure facilitates the alignment of the color filter and TFT dramatically.
Hitoshi WAKABAYASHI Takeshi ANDOH Tohru MOGAMI Toru TATSUMI Takemitsu KUNIO
A uniform raised-salicide technology has been investigated using both uniform selective-epitaxial-growth (SEG) silicon and salicide films, to reduce a junction leakage current of shallow source/drain (S/D) regions for high-performance CMOS devices. The uniform SEG-Si film without pits is formed by using a wet process, which is a carbon-free oxide removal only using a dilute hydrofluoric acid (DHF) dipping, prior to the Si-SEG process. After a titanium-salicide formation using a conventional two-step salicide process, this uniform SEG-Si film achieves good S/D junction characteristics. The uniform titanium-salicide film without bowing into a silicon is formed by a smaller Ti/SEG-Si thickness ratio, which results in a low sheet resistance of 5 Ω/sq. without a narrow-line effect. Furthermore, the drive current is maximized by this raised-salicide film using a Ti/SEG-Si thickness ratio of 1.0.
Koichiro MASHIKO Kimio UEDA Tsutomu YOSHIMURA Takanori HIROTA Yoshiki WADA Jun TAKASOH Kazuo KUBO
Based on the partially-depleted, thin-film SOI/CMOS technology, the influence of reduced junction capacitance on the performance of the elementary gates and large scale gate array chip is reviewed. To further reduce the power consumption, SOI-specific device configurations, in which the body-bias is individually controlled, are effective in lowering the supply voltage and hence the power consumption while keeping the circuit speed. Two attempts are introduced: (1) DTMOS (Dynamic-Threshold MOS)/SOI to achieve ultra low-voltage and yet high-speed operation, and (2) ABB (Active-Body-Bias) MOS to enhance the current drive under the low supply voltage.