To obtain a full picture of potential applications for propagation-delay based X channels, it is important to obtain all feasible schemes of cyclic interference alignment including the encoder, channel instance, and decoder. However, when the dimension goes larger, theoretical analysis about this issue will become tedious and even impossible. In this letter, we propose a computer-aided solution by searching the channel space and the scheduling space, which can find all feasible schemes in details. Examples are given for some typical X channels. Computational complexity is further analyzed.

Compared with the unicast scenario, X channels with multicast messaging can support richer transmission scenarios. The transmission efficiency of the wireless multicast X channel is an important and open problem. This article studies the degrees of freedom of a propagation-delay based multicast X channel with two transmitters and arbitrary receivers, where each transmitter sends K different messages and each receiver desires K - 1 of them from each transmitter. The cyclic polynomial approach is adopted for modeling and analysis. The DoF upper bound is analyzed and shown to be unreachable. Then a suboptimal scheme with one extra time-slot cycle is proposed, which uses the cyclic interference alignment method and achieves a DoF of K - 1. Finally, the feasibility conditions in the Euclidean space are derived and the potential applications are demonstrated for underwater acoustic and terrestrial radio communications.

Interference alignment (IA) in temporal domain is important in the case of single-antenna vehicle communications. In this paper, perfect cyclic IA based on propagation delay is extended to the K×2 X channels with two receivers and arbitrary transmitters K≥2, which achieves the maximal multiplexing gain by obtaining the theoretical degree of freedom of 2K/(K+1). We deduce the alignment and separability conditions, and propose a general scheme which is flexible in setting the index of time-slot for IA at the receiver side. Furthermore, the feasibility of the proposed scheme in the two-/three- Euclidean space is analyzed and demonstrated.

For the three-user X channel, its degree of freedom (DoF) 9/5 has been shown achievable theoretically through asymptotic model with infinite resources, which is impractical. In this article, we explore the propagation delay (PD) feature among different links to maximize the achievable DoF with the minimum cost. Since perfect interference alignment (IA) is impossible for 9 messages within 5 time-slots, at least one extra time-slot should be utilized. By the cyclic polynomial approach, we propose a scheme with the maximum achievable DoF of 5/3 for 10 messages within 6 time-slots. Feasibility conditions in the Euclidean space are also deduced, which demonstrates a quite wide range of node arrangements.

Long-distance wireless local area networks (WLANs) are the key enablers of wide-area and low-cost access networks in rural areas. In a WLAN, the long propagation delay between an access point (AP) and stations (STAs) significantly degrades the throughput and creates a throughput imbalance because the delay causes unexpected frame collisions. This paper summarizes the problems caused in the medium access control (MAC) mechanism of the WLAN by a long propagation delay. We propose a MAC protocol for solving the delay-induced throughput degradation and the throughput imbalance between the uplink and the downlink in WLANs to address these problems. In the protocol, the AP extends NAV duration of CTS frame to protect an ACK frame and transmits its data frame to avoid delay induced frame collisions by piggybacking on the ACK frame transmission. We also provide a throughput model for the proposed protocol based on the Bianchi model. A numerical analysis using the proposed throughput model and simulation evaluation demonstrate that the proposed protocol increases the system throughput by 150% compared with that obtained using the conventional method, and the uplink throughput can be increased to the same level as the downlink throughput.

We have investigated the low-power circuit applicability of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Based on the device-level comparison of HG, SiO2-only and high-k-only TFETs, their circuit performance and energy consumption have been discussed. It has been shown that HG TFETs can deliver 14400x higher performance than the SiO2-only TFETs and 17x higher performance than the high-k-only TFETs due to its higher on current and lower capacitance at the same static power, same power supply. It has been revealed that HG TFETs have better voltage scalability than the others. It is because HG TFETs dissipate only 8% of energy consumption of SiO2-only TFETs and 17% of that of high-k-only TFETs under the same performance condition.

This paper is concerned with the packet transmission scheduling problem for repeating all-to-all broadcasts in Underwater Sensor Networks (USN) in which there are n nodes in a transmission range. All-to-all communication is one of the most dense communication patterns. It is assumed that each node has the same size packet. Unlike the terrestrial scenarios, the propagation time in underwater communications is not negligible. We define all-to-all broadcast as the one where every node transmits packets to all the other nodes in the network except itself. So, there are in total n(n - 1) packets to be transmitted for an all-to-all broadcast. The optimal transmission scheduling is to schedule in a way that all packets can be transmitted within the minimum time. In this paper, we propose an efficient packet transmission scheduling algorithm for underwater acoustic communications using the property of long propagation delay.

In this letter, the effect of a propagation delay resulting from the use of an OFDM system with a transparent mobile multi-hop relay (MMR) is initially analyzed. Then, a least square (LS) channel estimation technique for the OFDM system with throughput enhancement (TE) MMR or cooperative MMR is proposed. It is demonstrated by computer simulation that the proposed LS channel estimation technique for OFDM systems with transparent MMR is superior to the conventional technique in terms of mean square error (MSE) and bit error rate (BER).

A simple analytical model based on Delayed Quadratic (DQ) Transfer Function approximation is proposed for estimating waveforms of inductive single-line interconnects in VLSI's. An expression for overshoot voltage is derived by the model within 17% error for the line width less than 10 times the minimum line width and typical input signal. A delay expression is also proposed within 15% for the same condition. The strength of the inductive effect is shown to be expressed by a closed-form expression, A=2(L(CT+0.5C))1/2/(RT(CT+CJ)+RTC+RCT+0.4RC). By using the criteria, a scaling trend of inductive effects in VLSI's is discussed. It is shown that the inductive effect of single-line, minimum-width VLSI interconnect peaks off at 90 nm based on the ITRS predicted parameters.

We have been investigating an orthogonal frequency division multiple access (OFDMA) based cellular system that is called "dynamic parameter controlled orthogonal frequency and time division multiple access (DPC-OF/TDMA)" for the development of beyond third generation (B3G) mobile communication systems. Moreover, we have already proposed a time alignment control (TAC) to compensate propagation delays that induce a multiple-access interference (MAI) in the uplink OFDMA. However, that TAC includes a large amount of computations. This means that it is quite difficult for the OFDMA systems to implement TAC into volume-limited hardware devices such as field programmable gate array (FPGA). Thus, we propose a new complexity-reduced TAC (CRTAC) in this paper. CRTAC can be implemented into such devices easily. In this paper, we show some computer simulation results, and then evaluate the error rate performances of DPC-OF/TDMA employing CRTAC. Moreover, we also show the benefit of the reasonable level of the implementation complexity made by CRTAC.

This paper proposes an analytical expression for the maximum operating frequency of an emitter-coupled-logic master-slave toggle flip-flop (ECL MS TFF) based on an impulse response method. The analytical expression was in good agreement with not only SPICE simulations, but also experimental values. The analytical expression also indicated that state-of-the-art InP-based heterojunction bipolar transistors have potential to achieve over 100-GHz operation in ECL MS TFFs. Also, the proposed method was applied to the maximum operating frequency of a source-coupled FET logic (SCFL) MS TFF.

We propose ATM switching nodes with a feedback rate control scheme, AREX, which does not require a large buffer space and does not deteriorate throughput even in large-scale and high-speed ATM-WANs. The goal of our study is to establish the ATM multi-protocol emulation network ALPEN, which is an ATM-WAN architecture for establishing a backbone for multimedia networks. ALPEN achieves an ATM-WAN which is robust against long propagation delays. It also provides high performance without a large buffer space in an ATM-WAN environment. In ALPEN, each transit node informs the edge nodes only its residual bandwidth ratio. The edge nodes support multiple ATM-layer services by emulating them based on the information notified by transit nodes. Our research has been directed towards achieving high performance ABR (Available Bit Rate) service in an ATM-WAN by using ALPEN. The conventional ABR service requires transit nodes to have relatively high calculation power and large buffer space to overcome the effect of the long propagation delays common in WANs. ALPEN node systems have been developed for trials with actual network traffic. ALPEN with AREX reduces the calculation load of transit nodes for ABR service. That is confirmed by the size of the DSP program created for a test system. ALPEN with AREX is, therefore, able to emulate ABR service with higher performance in ATM-WANs, because ALPEN edge nodes are able to indicate the users allowed by ER (Explicit Rate) feedback. The network throughput, maximum queue length at congestion point, and burst transmission rate are determined by simulation. ALPEN with AREX achieves better performances than the conventional ABR network.

We propose a propagation delay model for SRAM-based FPGAs. It is a simplified Elmore delay model with a linear fan-out function. Therefore, the computational complexity is small. In order to ensure calculation accuracy, the model parameters are extracted from real layout data. The average model error is 4% compared to actual delays. The model is applicable for delay estimation in a router and as a tool for static calculation of critical path delay.

A new adaptive rate control with congestion prediction is developed that is highly robust against long propagation delays. It minimizes the network performance degradation caused by the delay based on prediction by extrapolating past data and correction using new notification. The simulation results show that our proposed control maintains high throughput and a smaller buffer even in long propagation delay networks, like ATM-WAN.

This paper describes the fabrication of 0.1 µm gate length CMOS devices and analysis of delay time by circuit simulation. In order to reduce the gate resistance, TiN capped cobalt salicide technology is applied to the fabrication of 0.1 µm CMOS devices. Gate sheet resistance with a 0.1 µm gate is as low as 5 Ω/sq. Propagation delay times of 0.1 µm and 0.15 µm CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15 µm, intrinsic delay in CMOS devices is the main dalay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1 µm, each parasitic component and intrinsic delay have similar contributions on device speed due to the short channel effect. To improve delay time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times and simulation predicted a delay time of 28 ps is possible with 0.15 µm CMOS inverters.

The paper describes the design considerations, fabrication process and performance of the newly developed 1-K ECL gate array implemented with fully self-aligned AlGaAs/GaAs hoterojunction bipolar transistors (HBTs). This gate array consists of 960 three-input OR/NOR ECL basic gates. It contains about 7,600 transistors in a chip area 8.15-mm8.45-mm. The basic (FI=FO=1, wiring length L=0-mm) and loaded (FI=FO=3, L=1-mm) gates exhibit delay times of 33-ps and 82-ps, respectively, with 8.5-mW/gate power dissipation. From the measured values, fan-in, fan-out and wiring delay times of 9-ps/FI, 7-ps/FO and 17-ps/mm are estimated, respectively. These results are in good agreement with the designed results obtained using "SPICE" simulation.

Air-bridge metal interconnection technology is used for upper level power supply line interconnections in GaAs LSI's to reduce the signal propagation delay time. This technology reduces both parasitic capacitance between the signal line and the power supply line, and propagation delay in the signal line to about 10% and about 50%, respectively, compared to conventional 3-level interconnections without air-bridges. Under standard load conditions (FI=FO=2, length of load line=2 mm), the air-bridge technique leads to gate propagation delays which are about 60% of those in conventional interconnections. We fabricated 2.1-k gate Gate Arrays and 4-kb SRAM's using the air-bridge structure to interconnect power supply lines. For a Gate Array with 0.7 µm gate Buried P-layer Lightly Doped Drain (BPLDD) FET's, the typical gate propagation delay under standard load conditions was about 110 ps with a dissipation power of 1.4 mW/gate. SRAM's with 05 µm gate BPLDD's had typical access time (tacc) of 1.5 ns with a dissipation power of 700 mW/chip.