State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, thermo-optic glass/polymer waveguides are also reviewed briefly.

A novel zero-voltage-switched half-bridge converter is proposed. This converter achieves the zero-voltage switching while maintaining a constant frequency PWM control. Then the power conversion of high efficiency and low noise is realized at a higher switching frequency. In the experiment, a high efficiency of 83% is achieved for a low output voltage of 3.3 V, an output current of 30 A, and an input-voltage range of 200 to 400 V at the switching frequency of 400 kHz.

The showering arc waveforms generated when contact is being separate have poor reproducibility whose causes are not sufficiently clear. This paper describes that the contact surface conditions which change with the number of contact operations are deeply related to the showering arc waveforms. First, it is experimentally shown that the contacts' surface roughness increases with the number of contact operations, and the growth model of contact surface roughness is proposed based on the change of contact resistance for the number of contact operations. Second, the growth model of molten metal bridge is proposed based on the fact that the showering arc waveforms change with the number of contact operations and the evaluation indexes of showering arc are proposed.

A switched-capacitor Wien bridge oscillator and its automatic gain controller are discussed for low-frequency generation. The dc voltage Vs related to the amplitude of oscillation is obtained from the voltage differences in the frequency-determining arm. Theoretical analysis of the ripples in Vs is reported.

We present a high performance AlGaAs/GaAs power HBT with very low thermal resistance for digital cellular phones. Device structure with emitter air-bridge is utilized and device layout is optimized to reduce thermal resistance based on three-dimensional thermal flow analysis, and in spite of a rather thick substrate (100 µm), which achieved a low thermal resistance of 23/W for a multi-finger (440 µm240 fingers) HBT. This 40 finger HBT achieved power added efficiency (PAE) of over 53%, 29.1 dBm output power (Pout) and high associated gain (Ga) of 13.5 dB with 50 kHz adjacent channel leakage power (Padj) of less than -48 dBc under a 948 MHz π/4-shifted QPSK modulation with 3.4 V emitter-collector voltage. We also investigated the difference of RF performance between two bias modes (constant base voltage and current), and found which mode is adequate for each stage in several stage power amplifier for the first time.

It is necessery to investigate the buckling mechanism in order to obtaining good performance from various sensors composed of resistors and microbridges or membranes. Especially for flow sensors, a convex formed bridge has an advantage over a flat or concave bridge with respect to heat transfer coefficient. We have fabricated various shapes of bridges and have prepared SiNx sputtered films as the support films of microbridges and Pt sputtered or evaporated films as resistors. We have achieved deformation control for both the longitudinal axis and transverse axis of Pt/SiNx double layered microbridges by appropriate selection of the total residual stress of Pt/SiNx structures and of the stress gradient between the Pt film and SiNx film. The deformation direction of the longitudinal axis of bridges for the beam bridge (Type ) are all the same as that of cantilevers and may be predicted via the stress gradient between the Pt and SiNx filmes of the bridges. The deflection of the transverse axis of the table bridge supported by four beams (Type ) changes linearly with the total stress of the Pt/SiNx structure and the deformation changes for the transverse axis are the same as that of completely free films as predicted from the stress gradient between the Pt film and the SiNx film. The interesting result is that the deformation direction for the longitudinal axis of Type is opposite to that of Type with the same film structure. We discuss the reason for this opposition via differences in the progress of the anisotropic etching. We consider that this result will expand the range of manufacturable shapes and film structures of microbridges.

In this paper, we present an analysis of microstrip line with a trapezoidal dielectric ridge in multilayered media. The method employed in this characterization is called partial-boundary element method (p-BEM) which provides an efficient technique to the analysis of the structures with multilayered media. To improve the convergence of the Green's function used in the analysis with the P-BEM, we employ a technique based on a combination of the Fourier series expansion and the method of images. Treatment on convergence for the boundary integrals is also described. After this treatment, it requires typically one tenth or one hundredth of Fourier terms to obtain the same accuracy compared with the original Green's function. Numerical results are presented for two microstrip lines that have a trapezoidal dielectric ridge placed on a one-layered substrate and a two-layered substrate. These numerical results demonstrate the effects on the characteristics of the microstrip line due to the existence of the dielectric ridge as well as the second layer between the ridge and the fundamental substrate.

We have studied the performances of several types of vortex flow transistors including prototype flux flow transistors (FFTs), nanobridge vortex flow transistors (NBVFTs) based on a parallel array of nanobridges, planar Josephson vortex flow transistors (planar JVFTs) based on a parallel array of grain boundary Josephson junctions, and JVFTs with a stacked structure (stacked JVFTs). The NBVFTs had considerably higher magnetic field sensitivity and shorter response time than the FFTs. A flux-to-voltage transfer function V/φ of 2.6 m V/φo and a modulation depth of 0.5 mV were obtained for the NBVFT composed of 2 nanobridges, while the current gain was small. The temperature dependence of the device parameters (the dynamic resistance and the inductance) suggests that the surface barrier to the Abrikosov vortex entry into the nanobridge strongly contributes to the relatively large V/φ values. The response time of the nanobridge is estimated to be 5 ps. On the other hand, the JVFTs showed large current gains because of the small kinetic inductance of the Josephson junction. The planar JVFT composed of 3 Josephson junctions with an asymmetrical geometry showed a current gain of 2.2 at 4.2 K. Also, the stacked JVFT showed the current gain of 2.0, while the maximum value of V/φ was 210 µV/φo. The mutual inductance between the control line and the superconducting loop within the transistor was enhanced in the stacked JVFT. This enhancement may yield a short response time compared to that of the planar JVFT. When we apply these vortex flow transistors, we should take account of the properties peculiar to each transistor.

This paper proposes new algorithms for diagnosing (detection, identification and location) baseline multistage interconnection networks (MIN) as one of the basic units in a massively parallel system. This is accomplished in the presence of single and multiple faults under a new fault model. This model referred to as the geometric fault model, considers defective crossing connections which are located between adjacent stages, internally to the MIN (therefore, a fault corresponds to a physical bridge fault between two connections). It is shown that this type of fault affects the correct geometry of the network, thus requiring a different testing approach than previous methods. Initially, an algorithm which detects the presence of bridge faults (both in the single and multiple fault cases), is presented. For a single bridge fault, the proposed algorithm locates the fault except in an unique pathological case under which it is logically impossible to differentiate between two equivalent locations of the fault (however, the switching element affected by this fault is uniquely located). The proposed algorithm requires log2 N test vectors to diagnose the MIN as fault free (where N is the number of input lines to the MIN). For fully diagnosing a single bridge fault, this algorithm requires at most 2 log2 N tests and terminates when multiple bridge faults are detected. Subsequently, an algorithm which locates all bridge faults is given. The number of required test vectors is O(N). Fault location of each bridge fault is accomplished in terms of the two lines in the bridge and the numbers of the stages between which it occurs. Illustrative examples are given.

We describe the design, fabrication, and characteristics of a push-pull type ridged Ti:LiNbO3 optical modulator with two electrodes. The structure keeps microwave propagation loss low and enables a large interaction between microwaves and optical waves under the condition of velocity and impedance matching, resulting in a large modulation bandwidth and low driving voltage. Using this structure, we have developed an optical intensity modulator with an optical 3-dB bandwidth of 45 GHz (an electrical 3-dB bandwidth of 30 GHz) and a half-wave voltage of 3.9 V in single-electdoe operation (a half-wave voltage of 1.95 V in push-pull operation)at a wavelength of 1.55µm.

In this study, we propose a system of N Wien-bridge oscillators with the same natural frequency coupled by one resistor, and investigate synchronization phenomena in the proposed system. Because the structure of the system is different from that of LC oscillators systems proposed in our previous works, this system cannot exhibit N-phase oscillations but 3-phase and in-phase oscillations. Also in this system, we can get an extremely large number of steady phase states by changing the initial states. In particular, when N is not so large, we can get more phase states in this system than that of the LC oscillators systems. Because this system does not include any inductors and is strong against phase error this system is much more suitable for applications on VLSI compared with coupled system of van der Pol type LC oscillators.

Arc discharge between electrodes of relays and switches often causes contact surface damage through material transfer and arc erosion. Especially, material transfer sometimes occurs and brings serious failure even under lower load that is quite smaller than the minimum arc current value of contact material. In this paper, contact surface configuration, material transfer, and arc erosion characteristics of Ag and AgPd 60 contacts were experimentally studied after 0.5 or 1 million switching operations at various load levels. The followings can be made clear. Firstly, it was confirmed that the arcs and material transfer occurred even under such current that was lower than the minimum arc current. Therefore, the definition of the arc occurrence boundary current was newly determined. Secondly, the relation between load conditions (current and power supply voltage) and contact surface configuration (craters and pips) caused by material transfer was studied. The arc erosion behaviors of tested samples could be classified into two types: material transfer type and wear-out type. As one of the primary factors of transition from the former type to the latter one, contact activation was considered. The influences of load conditions and organic gas emitted from relay structure on arc characteristics was experimentally examined. The results indicated that load current greatly influenced the amount of material transfer and that power supply voltage affected the occurrence of the wear-out type significantly. The activation behavior of the contact surface could be found through observing the bridge voltage waveform.

Air-bridge metal interconnection technology is used for upper level power supply line interconnections in GaAs LSI's to reduce the signal propagation delay time. This technology reduces both parasitic capacitance between the signal line and the power supply line, and propagation delay in the signal line to about 10% and about 50%, respectively, compared to conventional 3-level interconnections without air-bridges. Under standard load conditions (FI=FO=2, length of load line=2 mm), the air-bridge technique leads to gate propagation delays which are about 60% of those in conventional interconnections. We fabricated 2.1-k gate Gate Arrays and 4-kb SRAM's using the air-bridge structure to interconnect power supply lines. For a Gate Array with 0.7 µm gate Buried P-layer Lightly Doped Drain (BPLDD) FET's, the typical gate propagation delay under standard load conditions was about 110 ps with a dissipation power of 1.4 mW/gate. SRAM's with 05 µm gate BPLDD's had typical access time (tacc) of 1.5 ns with a dissipation power of 700 mW/chip.