Mixed-signal integrated circuit design and simulation highly rely on behavioral models of circuit blocks. Such models are used for the validation of design specification, optimization of system topology, and behavioral synthesis using a description language, etc. However, automatic behavioral model generation is still in its early stages; in most scenarios designers are responsible for creating behavioral models manually, which is time-consuming and error prone. In this paper an automatic behavioral model generation method for switched-capacitor (SC) integrator is proposed. This technique is based on symbolic circuit modeling with approximation, by which parametric behavioral integrator model can be generated. Such parametric models can be used in circuit design subject to severe process variational. It is demonstrated that the automatically generated integrator models can accurately capture process variation effects on arbitrarily selected circuit elements; furthermore, they can be applied to behavioral simulation of SC Sigma-Delta modulators (SDMs) with acceptable accuracy and speedup. The generated models are compared to a recently proposed manually generated behavioral integrator model in several simulation settings.

This paper presents a system architecture for sensor signal digitization utilizing a band-pass sigma-delta modulator (BP ΣΔM). The first version of the proposed system architecture was implemented in 5 V 0.7 µm CMOS technology. The proposed system architecture is useful for our capacitive pressure sensor measurement. The paper describes the possibilities of using the proposed enhanced system architecture in impedance spectroscopy and in capacitive pressure sensor measurement. The BP ΣΔM is well suited for wireless applications. This paper shows another way how to use its advantages.

A 900 mV single-stage class-AB amplifier suitable for the Switched-Opamp technique is presented. To improve the slew-limited characteristics, a Dynamic Current Source (DCS) circuit which boosts the tail currents of the amplifier is proposed. The tail current of the proposed circuit is well defined and independent of technology parameters and supply variations. The tail current of the amplifier is 40 µA with zero differential voltages, while the maximum output current is nearly 900 µA. A single-loop 3rd order Σ-Δ modulator with the proposed amplifier was designed. For a 260 mV 15.625 kHz sinusoidal input signal, the simulated dynamic range of the modulator is 89 dB.

An on-chip CMOS preamplifier for direct signal readout from an electret capacitor microphone has been designed with high immunity to common-mode and supply noise. The Gm-Opamp-RC based high impedance preamplifier helps to remove all disadvantages of the conventional JFET based amplifier and can drive a following switched-capacitor sigma-delta modulator in order to realize a compact digital electret microphone. The proposed chip is designed based on 0.18 µm CMOS technology, and the simulation results show 86 dB of dynamic range with 4.5 µVrms of input-referred noise for an audio bandwidth of 20 kHz and a total harmonic distortion (THD) of 1% at 90 mVrms input. Power supply rejection ratio (PSRR) and common-mode rejection ration (CMRR) are more than 95 dB at 1 kHz. The proposed design dissipates 125 µA and can operate over a wide supply voltage range of 1.6 V to 3.3 V.

We have designed a superconductor-semiconductor hybrid analog-to-digital (A/D) converter and experimentally evaluated its performance at sampling frequencies up to 18.6 GHz. The A/D converter consists of a superconductor front-end circuit and a semiconductor back-end circuit. The front-end circuit includes a sigma-delta modulator and an interface circuit, which is for transmitting data signal to the semiconductor back-end circuit. The semiconductor back-end circuit performs decimation filtering. The design of the modulator was modified to reduce effects of integrator leak and thermal noise on signal-to-noise ratio (SNR). Using the improved modulator design, we achieved a bit-accuracy close to the ideal value. The hybrid architecture enabled us to reduce the integration scale of the front-end circuit to fewer than 500 junctions. This simplicity makes feasible a circuit based on a high TC superconductor as well as on a low TC superconductor. The experimental results show that the hybrid A/D converter operated perfectly and that SNR was 84.8 dB (bit accuracy~13.8 bit) at a band width of 9.1 MHz. This converter has the highest performance of all sigma-delta A/D converters.

For the purpose of reducing the quantization noise and power consumption of UWB-OFDM transceiver, a new time domain-based interpolator and decimator structure is proposed to realize five-bit D/A and A/D converters in the five-bit 128-tone sigma-delta modulation (SDM) UWB-OFDM transceiver. The five-bit 128-tone SDM UWB-OFDM transceiver using time domain-based interpolator and decimator in place of time spreader and de-spreader can obtain time-domain spread spectrum processing gain and reduce quantization noise simultaneously. The structure of the five-bit 128-tone SDM A/D converter, which employs 32 parallel analog SDM circuits without up-sampling, is designed. Simulation results demonstrate that BER of the proposed five-bit 128-tone SDM D/A and A/D converters based on time domain-based interpolator and decimator scheme can satisfy the performance requirements of the five-bit 128-tone SDM UWB-OFDM transceiver for the QPSK, 16-QAM and 64-QAM modulations.

In this paper, an ultra-low power variable-resolution sigma-delta (ΣΔ) modulator for biomedical application is presented. The resolution of proposed modulator can be adjusted by switching its sampling frequency and architecture. The architecture is switched between second-order single-loop modulator and fourth-order cascaded second stage noise shaped modulator to reach different resolution requirement. The proposed sigma-delta modulator is implemented by single phase integrators based on a fully differential switched-capacitor circuit. The digital cancellation logic is embedded in the chip so that it would easily be integrated with biomedical instrument for effective acquisition. Experimental results of the proposed variable-resolution ΣΔ modulator fabricated in standard CMOS 0.18 µm technology confirm the expected specifications from 65 dB signal-to-noise distortion to 96 dB with 1 kHz bandwidth and power consumption range from 48 µW to 360 µW with a 1.8 V battery supply.

A 1-V operational sigma-delta modulator with a second-order passive switched capacitor filter is designed and fabricated by using a 90 nm CMOS process. No gate-voltage bootstrapped scheme is adopted to drive analog switches, and the voltage gain of a comparator is chosen to be 94 dB. The experimental results show that the peak SNR reached 68.9 dB with a frequency bandwidth of 40 kHz when the clock was 40 MHz.

This paper proposes a jitter tolerant continuous-time sigma-delta A-D converter structure as well as its design method. This method transforms a conventionally designed sigma-delta A-D converter into a jitter tolerant one. Jitter tolerance is provided by the modified feedback signal paths and a consequently inserted digital LPF. This method is applicable independently of a system order and the other specifications.

A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.

In this paper, a low-voltage low-power sigma-delta modulator dedicated to implantable sensing devices is presented. This second-order single-loop sigma-delta modulator is implemented with half-delay integrators. These integrators are based on new fully-differential CMOS class AB switched-Operational Transconductance Amplifier (switched-OTA). An on-chip voltage doubler is introduced to locally boost a supply voltage at the input stage of a conventional OTA in order to allow rail-to-rail signal swing. Experimental results of the modulator fabricated in CMOS 0.18 µm technology confirm its expected features of a peak signal-to-noise ratio (SNR) of 72 dB, a signal-to-noise distortion ratio (SNDR) of 62 dB in a 5 kHz signal bandwidth, and a power consumption lower than 66 µW with a 900 mV voltage supply.

This paper proposes a new controlling technique of asynchronous sigma delta modulation with characteristic of one-cycle response. This technique can reject power source perturbations in one cycle period and reduce the peaks of harmonic with one side random hysteresis technique. The proposed method was analyzed, designed, and experimented in a full bridge inverter. The distortion of output voltage and the harmonic peaks were used to measure the performance of the proposed technique. The experimental results show that the proposed technique can reduce the peak of harmonic up to 0.42 p.u and the harmonic distortion 5.9% at the ripple of 20% of power source when comparing with convention asynchronous sigma delta modulation.

This paper presents a novel class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections. To demonstrate the efficiency of the proposed modulator architectures a prototype with HSPICE is implemented. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage is used to implement the fourth order modulator. Simulation results with OSR of 16 give signal to noise plus distortion ratio (SNDR) and dynamic range (DR) of 90-dB and 92.5-dB including the circuit noise in the 1.25-MHz signal bandwidth, respectively. The circuit is implemented in a 0.13-µm standard CMOS technology. It dissipates about 40-mW from a single 1.2-V power supply voltage.

We propose binary-quantized and spatio-temporally discretized network models of linear diffusion systems and investigate their filtering effect on single-bit sigma-delta (ΣΔ) modulated signals. The network consists of only one kind of elements that add ΣΔ modulated signals and quantize the sum in the form of single-bit signal. A basic one-dimensional network is constructed first. Then, the network is extended into two dimensions. These networks have characteristics equivalent to those of linear diffusion systems in both time and frequency domains. In addition, network noise caused by the quantization in the elements contains low-level low-frequency components and high-level high-frequency components. Therefore, the proposed networks have possibility to be used as signal propagation and diffusion media of ΣΔ domain filters.

This work presents a new sigma-delta modulator (SDM) architecture for a wide bandwidth receiver. This architecture contains dual-bandwidth for W-CDMA and GSM system applications. Low-distortion swing-suppressing SDM and interpolative SDM cascaded units are used together. Using the low-distortion swing-suppressing technique, the resolution can be improved even under non-linearity effects. The interpolative SDM extends the signal bandwidth and represses the high-band noise. The SDM used in the W-CDMA and GSM applications was designed and simulated using 0.25-µm 1P5M CMOS technology. The simulated peak SNDR of W-CDMA and GSM are 72/70 dB and 82/84 dB in Low-IF/Zero-IF standards.

In this paper, a novel methodology for designing and analyzing high performance sigma-delta leapfrog modulators for ultra-high resolution analog-to-digital (A/D) converters is presented. The less sensitive topology, the leapfrog topology, in component variations is analyzed by considering the noise transfer function (NTF). By using theoretical analysis, the loop coefficients are constrained to a small, clear and definite range called the stable region (SR). With the output voltage limited within 2 V, an absolutely stable region (ASR) is obtained. A program that analyzes and generates the required coefficients is constructed for easily designing this topology. For a 256 over-sampling ratio (OSR) and the coefficients from ASR, the signal to noise ratio (SNR) and dynamic range (DR) are 105 dB and 100 dB, respectively. In accordance with the behavior simulation results, the system is not only stable and efficient but also suitable for high-resolution applications.

This letter presents a simple A/D converter based on the circle map. The converter encodes a dc input into a binary output sequence and has the trapping window that extracts an available part of the output sequence. Using the available part, the decoder provides an estimation by a fraction with variable denominator: it can realize higher resolution. Theoretical evidences for the estimation characteristics are given.

Piecewise linear (PWL) circuit modules operating on sigma-delta (ΣΔ) modulated signals and nonlinear signal processors built of these modules are proposed. The proposed module library includes absolute circuits, min/max selectors and negative resistances. Their output signal-to-noise ratio is higher than 50dB when their oversampling ratio is 28. A nonlinear filter and a stochastic resonator are presented as applications of the PWL modules to ΣΔ domain signal processing. The filter is structured with 37% of logic gates consumed by an equivalent filter with a 5-bit parallel signal form.

The capability of a high-temperature superconducting sigma-delta modulator was studied by means of circuit simulation and FFT analysis. Parameters for the circuit simulation were extracted from experimental measurements. The present circuit simulation includes thermal-noise effect. Successive FFT analyses were made to evaluate the dynamic range of the sigma-delta modulator. As a result, the dynamic range was evaluated as 60.1 dB at temperature of 20 K and 56.9 dB at temperature of 77 K.

A digital circuit technique is proposed to process directly bit-stream signals from analog-to-digital converters based on sigma-delta modulation. Newly developed adder and multiplier are fundamental circuit modules for the processing. Using the fundamental modules and up/down counters, other circuit modules such as divider and square root circuits are also realized. The signal processors built of the modules have advantages over multi-bit Nyquist rate processors in circuit scale by the following two distinct features: First, single-bit/multi-bit converters are not needed at the inputs of the processors because the arithmetic modules directly process bit-stream signals. Secondly, the arithmetic modules consist of small number of logic gates. As an application of the technique to digital signal processing for communications, a QPSK demodulator is presented. The demodulator is structured with 40% of logic gates consumed by an equivalent multi-bit demodulator.