SiC-MOSFETs are being increasingly implemented in power electronics systems as low-loss, fast switching devices. Despite the advantages of an SiC-MOSFET, its large dv/dt or di/dt has fear of electromagnetic interference (EMI) noise. This paper proposes and demonstrates a simple and robust gate driver that can suppress ringing oscillation and surge voltage induced by the turn-off of the SiC-MOSFET body diode. The proposed gate driver utilizes the channel leakage current methodology (CLC) to enhance the damping effect by elevating the gate-source voltage (VGS) and inducing the channel leakage current in the device. The gate driver can self-adjust the timing of initiating CLC operation, which avoids an increase in switching loss. Additionally, the output voltage of the VGS elevation circuit does not need to be actively controlled in accordance with the operating conditions. Thus, the circuit topology is simple, and ringing oscillation can be easily attenuated with fixed circuit parameters regardless of operating conditions, minimizing the increase in switching loss. The effectiveness and versatility of proposed gate driver were experimentally validated for a wide range of operating conditions by double and single pulse switching tests.

With the advantages of higher blocking voltage, higher operation temperature, fast-switching characteristics, and lower switching losses, the silicon carbide (SiC) MOSFET has attracted more attentions and become an available replacement of traditional silicon (Si) power semiconductor in applications. Despite of all the merits above, electromagnetic interference (EMI) issues will be induced consequently by the ultra-fast switching transitions of the SiC MOSFET. To quickly and precisely assess the switching behaviors of the SiC MOSFET for EMI investigation, an analytical model is proposed. This model has comprehensively considered most of the key factors, including parasitic inductances, non-linearity of the junction capacitors, negative feedback effect of Ls and Cgd shared by the power and the gate stage loops, non-linearity of the trans-conductance, and skin effect during voltage and current ringing stages, which will considerably affect the switching performance of the SiC MOSFET. Additionally, a finite-state machine (FSM) is especially utilized so as to analytically and intuitively describe the switching behaviors of the SiC MOSFET via Stateflow. Based on double pulse test (DPT), the effectiveness and correctness of the proposed model are validated through the comparison between the calculated and the measured waveforms during switching transitions. Besides, the model can appropriately depict the spectrum of the drain-source voltage of the MOSFET and is suitable for EMI investigation in applying of SiC devices.

In this paper, Epitaxial (Epi) Junction Termination Extension (JTE) technique for silicon carbide (SiC) power device is presented. Unlike conventional JTE, the Epi-JTE doesn't require high temperature (about 500°C) implantation process. Thus, it doesn't require high temperature (about 1700°C) process for implanted dose activation and surface defect curing. Therefore, the manufacturing cost will be decreased. Also, the fabrication process is very simple because the dose of the JTE is controlled by epitaxy growth. The blocking characteristic is analyzed through 2D-simulation for the proposed Epi-JTE. In addition, the effect was validated by experiment of fabricated SiC device with the Single-Zone-Epi-JTE. As a result, it has blocking capability of 79.4% compared to ideal parallel-plane junction breakdown.

We investigated the effects of various field plate and buried gate structures on the DC and small signal characteristics of 4H-silicon carbide (SiC) metal-semiconductor field-effect transistors (MESFETs). In comparison with the source-connected field plate, the gate-connected field plate exhibited superior frequency response while having similar DC characteristics. In order to further enhance the output power, dual field plates were employed in conjunction with a buried gate structure.

We designed and fabricated 4H-SiC PIN avalanche photodiodes (APD) for UV detection. The thickness of an intrinsic layer in a PIN structure was optimized in order to achieve the highest quantum efficiency at the wavelength of interest. The optimized 4H-SiC PIN APDs exhibited a maximum external quantum efficiency of >80% at the wavelength of 280 nm and a gain greater than 40000. Both electrical and optical characteristics of the fabricated APDs were in agreement with those predicted from simulation.

This paper will review the development of SiC power devices especially SiC power junction field-effect transistors (JFETs). Rationale and different approaches to the development of SiC power JFETs will be presented, focusing on normally-OFF power JFETs that can provide the highly desired fail-save feature for reliable power switching applications. New results for the first demonstration of SiC Power ICs will be presented and the potential for distributed DC-DC power converters at frequencies higher than 35 MHz will be discussed.

Hetero-interface properties of SiO2/4H-SiC on (0001), (11-20), and (03-38) crystal orientations are presented. Epitaxial growth on new crystal orientations, (11-20) and (03-38), is described by comparing with the growth on (0001). Using thermal oxidation with wet oxygen, metal-oxide-SiC (MOS) structure was fabricated. From high-frequency capacitance-voltage characteristics measured at 300 K and 100 K, the interface properties were characterized semi-quantitatively. The interface state density was precisely determined using the conductance method for the MOS structure at 300 K. The new crystal orientations have the lower interface state density near the conduction band edge than (0001). From the characteristics of inversion-type planar MOSFETs, higher channel mobilities were obtained on (03-38) and (11-20) than on (0001). The cause of the difference in the channel mobility is speculated by the difference bond configuration of the three crystal orientations.