Routing protocols are a critical component in IP networks. Among these, the Open Shortest Path First (OSPF) has been a widely used routing protocol in IP networks for some years. Beside dedicated hardware, a great interest on routing systems based on open software is raising among Internet Service Providers. Many open source implementations of this protocol have been developed, among which GNU Zebra is one of the most complete. In this paper we perform a study of the performances of the Shortest Path First computation in GNU Zebra, as prescribed by the Internet Engineering Task Force, and we provide a comparison between a Cisco 2621 access router and a PC-based router equipped with routing software GNU Zebra. Moreover we describe a set of modifications made on the GNU Zebra code in order to optimize some processes, whose algorithms were not efficient and whose experimental measures had showed a lack of optimization, thus finally obtaining performances better than the one measured on commercial systems.

According to the proliferation of ubiquitous computing, various products which contain large-size embedded software have been developed. One of most typical features of embedded software is concurrency of software and hardware factors. That is, software has connected deeply into hardware devices. The existence of various hardware make quality assurance of embedded software more difficult. In order to assure quality of embedded software more effectively, this paper discusses features of embedded software and an effective method for quality assurance for embedded software. In this paper, we first analyze a failure distribution of embedded software and discuss the effects of hardware devices on quality of embedded software. Currently, in order to reduce hardware related faults, huge effort for testing with large number of test items is required. Thus, one of the most important issues for quality assurance of embedded software is how to reduce the cost and effort of software testing. Next, focusing on hardware constraints as well as software specifications in embedded software, we propose an evaluation metrics for determinating important functions for quality of embedded software. Furthermore, by referring to the metrics, undesirable behaviors of important functions are identified as root nodes of fault tree analysis. From the result of case study applying the proposed method to actual project data, we confirmed that test items considering the property of embedded software are constructed. We also confirmed that the constructed test items are appropriate to detect hardware related faults in embedded systems.

Recently, software development projects have been required to produce highly reliable systems within a short period and with low cost. In such situation, software quality prediction helps to confirm that the software product satisfies required quality expectations. In this paper, by using a Bayesian Belief Network (BBN), we try to construct a prediction model based on relationships elicited from the embedded software development process. On the one hand, according to a characteristic of embedded software development, we especially propose to classify test and debug activities into two distinct activities on software and hardware. Then we call the proposed model "the BBN for an embedded software development process". On the other hand, we define "the BBN for a general software development process" to be a model which does not consider this classification of activity, but rather, merges them into a single activity. Finally, we conducted experimental evaluations by applying these two BBNs to actual project data. As the results of our experiments show, the BBN for the embedded software development process is superior to the BBN for the general development process and is applicable effectively for effective practical use.

A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the timing constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given timing constraint. We expect that we can obtain processor core configurations of smaller area in the same timing constraint rather than a conventional system. The promising experimental results are also shown.

This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.

In this paper an analog-digital signal processing scheme for multichannel signal reception with low-IF receivers is proposed and its performance is investigated. In the low-IF receivers, the signal in the mirror frequency causes interference to the desired signal. In the proposed analog-digital signal processing scheme, the interference signal is extracted with the analog filter and the interference to the desired signal is reconstructed by LMS algorithm.

Process-centered software engineering environments (PSEEs) facilitate controlling complicated software processes. Traditional PSEEs are generally centrally controlled, which may result in the following drawbacks: (1) the server may become a bottleneck and (2) when the server is down, processes need to be suspended. To overcome the drawbacks, we developed a decentralized process engine ADPE (agent-based decentralized process engine). ADPE can be embedded in any PSEE to decentralize the PSEE. This paper presents ADPE.

In a ubiquitous computing environment, people are surrounded by hundreds of mobile or embedded computers each of which may be used to support one or more user applications due to limitations in their individual computational capabilities. We need an approach to coordinating heterogeneous computers that acts as a virtual computer around a mobile and ubiquitous computing environment and supports various applications beyond the capabilities of single computers. This paper presents a framework for building and aggregating distributed applications from one or more mobile components that can be dynamically deployed at mobile or stationary computers during the execution of the application. Since the approach involves mobile-transparent communications between components and component relocation semantics, it enables a federation of components to adapt its structure and deployment on multiple computers whose computational resources, such as input and output devices, can satisfy the requirement of the components in a self-organized manner. This paper also describes a prototype implementation of the approach and its application.

As the code division multiple access (CDMA) based third generation cellular infrastructure requires high performance signal processing in a baseband modem, an application-specific integrated circuit or a field-programmable gate array has commonly been used for chip rate processing. In this paper, the use of digital signal processors (DSP) is explored for a cdma2000 and a wideband CDMA channel modem with the goal of increasing flexibility. The design concepts of the prototype software-defined radio platform we implemented to estimate the potential and feasibility of commercial SDR platforms are presented. We discuss the hardware and software architecture of the platform, considerations for reconfigurability, and the test results. We also address practical issues for real-time chip rate processing and optimization schemes of DSP software, and provide detailed measurement results of DSP performance.

Process-centered software engineering environments (PSEEs) facilitate controlling software processes. Many issues related to PSEEs such as process evolution support have been addressed. We identify an unsolved issue, which is preventing information leakage when the process is being enacted. We developed a model called PsACL for the prevention. This paper proposes PsACL, which offers the following features: (a) controlling both read and write access of software products, (b) preventing indirect information leakage, (c) managing role associations, (d) managing role hierarchies, (e) enforcing static and simple dynamic separation-of-duty constraints, (f) allowing declassification of products, and (g) allowing access control information exchange among software processes.

Many computer systems are designed to make it easy for end-users to install and update software. An undesirable side effect, from the perspective of many software producers, is that hostile end-users may analyze or tamper with the software being installed or updated. This paper proposes a way to avoid the side effect without affecting the ease of installation and updating. We construct a computer system M with the following properties: 1) the end-user may install a program P in any conveniently accessible area of M; 2) the program P contains encoded instructions whose semantics are obscure and difficult to understand; and 3) an internal interpreter W, embedded in a non-accessible area of M, interprets the obfuscated instructions without revealing their semantics. Our W is a finite state machine (FSM) which gives context-dependent semantics and operand syntax to the encoded instructions in P; thus, attempts to statically analyze the relation between instructions and their semantics will not succeed. We present a systematic method for constructing a P whose instruction stream is always interpreted correctly regardless of its input, even though changes in input will (in general) affect the execution sequence of instructions in P. Our framework is easily applied to conventional computer systems by adding a FSM unit to a virtual machine or a reconfigurable processor.

In order to respond to the active market's needs for software with various new functions, the system testing must be completed within a limited period. Additionally, important faults, which are closely related to essential functions for users or the target system, have to be removed, preferably in system testing. Many techniques have been proposed to date for effective software testing. Among them, selective software testing is one of the most cost effective techniques. However, most of the previous techniques cannot be applied to short-term development and initial development of software with various new functions because much cost is needed for their testing preparation. In this paper, we propose a new method for selective system testing in which priorities assigned to functions play an essential role in the execution of testing. The priorities are determined based on the evaluation results of three metrics for functions: the frequency of use, the complexity of use scenario, and the fault impact to users. Detailed testing instructions are assigned to test items with high priority, and short and ordinal instructions are assigned to those with low priority. The difference in the volume of testing instruction controls the effort of checking test items. As a result of experimental application to actual software testing in a certain company, we have confirmed that the proposed selective system testing can detect both fatal faults related to key functions and critical faults for the system.

A very long instruction word (VLIW) digital signal processor (DSP), called ODiN, which could execute six instructions in a single cycle simultaneously, is designed and fabricated using 0.25 µm 1-ploy 5-metal standard cell static CMOS process. The ODiN core delivers maximum 600 MIPS with 100 MHz system clock. In order to achieve high performance operation, the designed core includes compact register files, orthogonal instruction set, single cycle operations for most instructions, and parallel processing based on software scheduling. In addition, a Viterbi decoder processor and a FFT processor that are embedded make it possible to implement software defined radio (SDR) applications efficiently.

This paper discusses the implementation of multi-band digital intermediate frequency (IF) for wideband CDMA (W-CDMA) transceiver. The majority of the implemented module in hardware is composed of wideband analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and field programmable-gated-arrays (FPGA). And in software, it is coded by VHSIC hardware description language (VHDL) for realizing digital filters and numerically controlled oscillator, etc. To cope with the hardware limitation such as the number of gates in FPGA, the overall digital filter embedded in transceiver is constructed via a cascading a series of decimation and interpolation filters. At transmitter, in order to upconvert the multi-band baseband channels simultaneously, two-stage digital complex quadrature modulation (DCQM) is utilized. The relevant up-and-down conversion of the numerically controlled oscillator (NCO) is designed in the form of a look-up-table (LUT), having samples associated with a sampled sinusoidal with period of 1/4. At receiver, to avoid the usage of surface acoustic wave (SAW) filter, the high-performance digital filter is implemented subject to satisfying band rejection ratio prescribed in blocker and adjacent channel specification. This paper provides the performance of the implemented digital IF module by revealing the results taken from the measurement instruments. Moreover, to confirm its validity computer simulations are simultaneously conducted.

For an efficient software download in cellular CDMA systems, location dependant session admission control (LDSAC) is presented. In the LDSAC scheme, a mobile that is located near cell center can request software download session, but the mobile that is located far from cell center can request session only after approaching near the cell center. Performance is analyzed in terms of handoff rate, mean channel holding time, session blocking probability and handoff forced termination probability. Numerical results show handoff rate between cells in the proposed scheme is reduced to 30-250% compared to conventional scheme, according to traffic characteristics such as terminal speed, session duration time and the size of the allowable zone area in a cell for the initiation of the session. And new session blocking probability decreases slightly, but handoff session forced termination probability decreases drastically.

An RF front-end using a six-port circuit is a promising technology for realization of a compact software defined radio (SDR) receiver. Such a receiver, called a six-port direct conversion receiver (DCR), consists of analog circuit and digital signal processing components. The six-port DCR itself outputs four different linear combinations of received and local signals. The output powers are measured at each port, and the received signal is recovered by solving a set of linear equations. This receiver can easily cover a wide frequency band unlike the conventional DCR since it does not require the precise orthogonality that the conventional one does. In this paper, we propose a novel calibration method for a six-port system that includes nonlinear circuits such as diode detectors. We demonstrated the demodulation performance of a six-port DCR by computer simulation and experiments at 1.9, 2.45, and 5.85 GHz.

Research in smart antenna technology has progressed over the past few years and is gradually reaching the phase of practical use. We have developed a smart antenna test bed for wireless local area network (LAN) that is based on the IEEE802.11b. The objective is to improve anti-multipath fading performance and expand communication distance. Using this test bed, we carried out field tests in two environment. One environment is an office in an non line of sight (NLOS), and another environment is an outdoor in a line of sight (LOS). In this paper, we explain the outline of the test bed, the measurement method, and present the results of the field tests. In the office environment, we measured the performance of each set with a different number of antenna elements. The results show that the dead-spots where communication becomes impossible disappear if the number of antenna elements is more than or equal to two. In addition, a greater number of elements indicates better performance. The total average throughput is 1.6 times as efficient when two elements are used, and 1.9 times when four elements are used. Cold spots where the throughput is slower than 1 Mbps are reduced by 80-90%. In the outdoor LOS environment field test, it is shown that by using four-element smart antenna for both transmitter and receiver, the communication distance reached 1km with an average throughput of 4 Mbps. These results prove that the smart antenna drastically improves the performance of a wireless LAN system, i.e. the IEEE802.11b.

Software rejuvenation is a preventive and proactive solution that is particularly useful for counteracting the phenomenon of software aging. In this paper, we consider both the periodic and non-periodic software rejuvenation policies under different dependability measures. As is well known, the steady-state system availability is the probability that the software system is operating in the steady state and, at the same time, is often regarded as the mean up rate in the system operation period. We show that the mean up rate should be defined as the mean value of up rate, but not as the mean up time per mean operation time. We derive numerically the optimal software rejuvenation policies which maximize the steady-state system availability and the mean up rate, respectively, for each periodic or non-periodic model. Numerical examples show that the real mean up rate is always smaller than the system availability in the steady state and that the availability overestimates the ratio of operative time of the software system.

Under current radio regulations, it is illegal to change the configuration of a radio after its type approval has been acquired. However, the reconfigurability of a Software Defined Radio (SDR) terminal, which is one of its benefits, is possible by changing its software in the field. This contradicts current radio regulations. Therefore, a new authorization procedure is necessary for system reconfiguration using SDR. It is necessary to satisfy the radio regulation. In other words, a new authorization procedure requires techniques to prevent the operation out of the allowed limits of SDR in the field. In this paper, we propose a novel mechanism, called Automatic Certification System (ACS), as a solution to these regulatory issues for SDR. The ACS is a system which gives type approval automatically to the software which affects the output power, central frequency, frequency band, modulation type and which controls analog circuits on an SDR terminal. We also propose the ACS based framework which aims to distribute the burden of the software manufacturer, hardware manufacturer, and governmental authority. After that, we describe the inspection method and discuss the case of a modulation scheme which can be Phase Shift Keying (PSK) or Minimum Shift Keying (MSK) schemes. Our simulations confirm that the ACS is able to certify the modulation software at the terminal.

A large body of research in the measurement of software complexity at code level has been conducted, but little effort has been made to measure the architectural-level complexity of a software system. In this paper, we propose some architectural-level metrics which are appropriate for evaluating the architectural attributes of a software system. The main feature of our approach is to assess the architectural-level complexity of a software system by analyzing its formal architectural specification, and therefore the process of metric computation can be automated completely.