A coplanar type lumped-element 6-pole microwave Chebyshev bandpass filter (BPF) of center frequency (f0) 2.0 GHz and fractional bandwidth (FBW) 1.0 % was designed. For the design method, theory of direct coupled resonator filters using K-inverters was employed. Coplanar type lumped-element BPFs are composed of a meander-line L and interdigital C elements. The frequency response was simulated and analyzed using an electromagnetic field simulator (Sonnet-EM). Further, the changes in f0 and FBW of the BPF were also realized by the mechanical tuning method.

FPGAs (Field-Programmable Gate Arrays) have been widely used as coprocessors to boost the performance of data-intensive applications [1],[2]. However, there are several challenges to further boost FPGA performance: the communication overhead between the host workstation and the FPGAs can be substantial; large-scale applications cannot fit in a single FPGA because of its limited capacity; mapping an application algorithm to FPGAs still remains a daunting job in configurable system design. To circumvent these problems, we propose in this paper the FPGA-based Hierarchical-SIMD (H-SIMD) machine with its codesign of the Pyramidal Instruction Set Architecture (PISA). PISA comprises high-level instructions implemented as FPGA functions of coarse-grain SIMD (Single-Instruction, Multiple-Data) tasks to facilitate ease of program development, code portability across different H-SIMD implementations and high performance. We assume a multi-FPGA board where each FPGA is configured as a separate SIMD machine. Multiple FPGA chips can work in unison at a higher SIMD level, if needed, controlled by the host. Additionally, by using a memory switching scheme and the high-level PISA to partition applications into coarse-grain tasks, host-FPGA communication overheads can be hidden. We enlist the two-dimensional Fast Fourier Transform (2D FFT) to test the effectiveness of H-SIMD. The test results show sustained high performance for this problem. The H-SIMD machine even outperforms a Xeon processor for this problem.

We describe three types of software-defined-radio (SDR) receivers based on superconducting technologies. The superconducting analog bandpass filters are essential for all types of the receivers. Another key component is an analog-to-digital converters (ADCs), which are required to have high resolution with a broad band width. The complementary Δ ADC based on the single-flux-quantum circuit is a promising candidate for the SDR receivers because it has a practical nature together with above-mentioned requirements. The experimentally obtained signal-to-noise ratio (SNR) and sensitivity, which are closely related to the resolution, are 34 dB and 20 µA for a quarter of the full-scale input with a band width of about 20 MHz. If we use the optimum decimation filter, the ADC is expected to have the SNR of 82 dB and the sensitivity of 300 nA. These values meet the requirements of the easiest type of the SDR receiver. After new fabrication process has been introduced and the architecture of the ADC has been improved, all types of recievers could be realized based on superconductors.

This paper studies the state-of-the-art software optimization methodology for symmetric cryptographic primitives on Pentium III and 4 processors. We aim at maximizing speed by considering the internal pipeline architecture of these processors. This is the first paper studying an optimization of ciphers on Prescott, a new core of Pentium 4. Our AES program with 128-bit key achieves 251 cycles/block on Pentium 4, which is, to our best knowledge, the fastest implementation of AES on Pentium 4. We also optimize SNOW2.0 keystream generator. Our program of SNOW2.0 runs at the rate of 2.75 µops/cycle on Pentium III, which seems the most efficient code ever made for a real-world cipher primitive. Our another interest is to optimize cryptographic primitives that essentially utilize 64-bit operations on Pentium processors. For the first example, the FOX128 block cipher, we propose a technique for speeding-up by interleaving two independent blocks using a register group separation. For another examples, we consider fast implementation of SHA512 and Whirlpool. It will be shown that the new SIMD instruction sets introduced in Pentium 4 excellently contribute to fast hashing of SHA512.

In this paper, we propose a new software reliability growth model which is the mixture of two exponential reliability growth models, one of which has the reliability growth and the other one does not have the reliability growth after the software is released upon completion of testing phase. The mixture of two such models is characterized by a weighted factor p, which is the proportion of reliability growth part within the model. Firstly, this paper discusses an optimal software release problem with regard to the expected total software cost incurred during the warranty period under the proposed software reliability growth model, which generalizes Kimura, Toyota and Yamada's (1999) model with consideration of the weighted factor. The second main purpose of this paper is to apply the Bayesian approach to the optimal software release policy by assuming the prior distributions for the unknown parameters contained in the proposed software reliability growth model. Some numerical examples are presented for the purpose of comparing the optimal software release policies depending on the choice of parameters by the non-Bayesian and Bayesian methods.

Long running software systems are known to experience an aging phenomenon called software aging, one in which the accumulation of errors during the execution of software leads to performance degradation and eventually results in failure. To counteract this phenomenon a proactive fault management approach, called software rejuvenation, is particularly useful. It essentially involves gracefully terminating an application or a system and restarting it in a clean internal state. In this paper, we evaluate dependability performance of a communication network system with the software rejuvenation under the assumption that the requests arrive according to a Markov modulated Poisson process (MMPP). Three dependability measures, steady-state availability, loss probability of requests and mean response time on tasks, are derived through the hidden Markovian analysis based on the time-based software rejuvenation scheme. In numerical examples, we investigate the sensitivity of some model parameters to the dependability measures.

This letter describes an efficient architecture for a Software Defined Radio (SDR) Wideband Code Division Multiple Access (WCDMA) receiver using for high performance wireless communication systems. The architecture is composed of a Radio Frequency (RF) front-end, an Analog-to-Digital Converter (ADC), and a Quadrature Amplitude Modulation (QAM) demodulator. A coherent demodulator, with a complete digital synchronization scheme, achieves the bit-error rate (BER) of 10-6 with the implementation loss of 0.5 dB for a raw Quadrature Phase Shift King (QPSK) signal.

In recent years, considerable attention has been devoted to continuously running software systems whose performance characteristics are smoothly degrading in time. Software aging often affects the performance of a software system and eventually causes it to fail. A novel approach to handle transient software failures due to software aging is called software rejuvenation, which can be regarded as a preventive and proactive solution that is particularly useful for counteracting the aging phenomenon. In this paper, we focus on a high assurance software system with fault-tolerance and preventive rejuvenation, and analyze the stochastic behavior of such a highly critical software system. More precisely, we consider a fault-tolerant software system with two-version redundant structure and random rejuvenation schedule, and evaluate quantitatively some dependability measures like the steady-state system availability and MTTF based on the familiar Markovian analysis. In numerical examples, we examine the dependence of two fault tolerant techniques; design and environment diversity techniques, on the system dependability measures.

This paper proposes two space-time joint channel parameter estimation and signal detection algorithms for downlink DS-CDMA systems with multiple-input-multiple-output (MIMO) wireless multipath fading channels. The proposed algorithms initially use the space-time MUSIC to estimate the DOA-delays of the multipath channel. Based on these estimated DOA-delays, a space-time channel decoupler is developed to decompose the multipath downlink channel into a set of independent parallel subchannels. The fading amplitudes of the multipath can then be estimated from the eigen space of the output of the space-time channel decoupler. With these estimated channel parameters, signal detection is carried out by a maximal ratio combiner on a pathwise basis. Computer simulations show that the proposed algorithms outperform the conventional space-time RAKE receiver while having the similar performance compared with the space-time minimum mean square error receiver.

In software defined radio systems, placing the analog-to-digital converter (ADC) near the antenna part in the block diagram of the receiver is desired to improve the flexibility of the system. The radio frequency (RF) sampling method, in which the received signal is sampled at the RF stage, realizes such structure. The undersampling is a potential method to sample the RF signal using the existing consumer ADCs because high speed ADCs are required in the traditional methods, such as Nyquist sampling or the oversampling of the RF signal. This paper presents a technique to determine the minimum sampling frequency to undersample the separated multiple wireless systems simultaneously. In addition, this paper proposes a frequency selecting scheme that enables selection of a lower sampling frequency by receiving at least the desired transmission channels in the wireless system signals. This paper also provides a result of performance analysis of the proposed scheme.

Improving GPS positioning accuracy requires an understanding of the inner workings of GPS receivers. However, the necessary hardware and software for research is prohibitively expensive. It is almost impossible to modify the correlator and functions of signal acquisition and tracking in commercial GPS hardware. The software GPS receiver allows us to access the inner workings of the receiver without significant time or expense. The present paper introduces a prototype software GPS receiver developed by us, which consists of a commercial RF-module and PC-based signal processing software. In addition, the software GPS receiver is shown herein to enable evaluation and mitigation of the code multipath error with the outputs of a software multi-correlator, which can be implemented easily in a software GPS receiver, with the aid of maximum likelihood criteria.

In this paper, we propose a new concept of receiver structure with diversity reception technique to realize multi-service simultaneous reception, which shares diversity branches between receiving communication services. In the proposed receiver structure, each diversity branch selects the receiving services dynamically according to channel states, and each communication service is always selected by at least one branch to realize multi-service simultaneous reception. A basic algorithm is also described to select combinations of a diversity branch and a receiving communication service. The total number of branches decreases and the effective number of branches per communication service increases, by sharing the branches between communication services in the proposed receiver. Simulation results are shown that the proposed diversity receiver achieves both complexity reduction and performance improvement.

The next-generation wireless networks will bring users with Software Defined Radio (SDR) terminals seamless mobility and ubiquitous computing through heterogeneous networks. This paper proposes a soft-prioritization based system selection algorithm performed by SDR terminal and investigates the effectiveness of the soft-prioritization based system selection by using a concrete simulation model. To maximize the quality of service (QoS), wireless communication systems are prioritized on the basis of criteria for system selection such as data rate, channel quality and cost, and should be dynamically changed. However, frequent inter-system handovers based on hard-prioritization are undesirable in view of interrupting and dropping, particularly for real-time traffic and managing channel capacities. Wireless communication systems are softly prioritized in the soft-prioritization based system selection algorithm, and therefore inter-system handovers between systems with the same priority aren't initiated. To elucidate the validity of the soft-prioritization based system selection algorithm, a system simulation model consisting of five wireless communication systems is employed. Simulation results confirm that the soft-prioritization system selection algorithm offers higher performance in terms of the number of inter-system handovers and throughput of best effort traffic.

Software defined radio (SDR) mobile terminals that can access multiple wireless communication systems are the trend of the future. An SDR wideband mobile terminal must be capable of high-speed data processing and low power consumption. We focused on reconfigurable processors with these features. To evaluate the performance of reconfigurable processors for SDR wideband mobile terminals, we developed and evaluated software that runs on a reconfigurable processor for the IEEE 802.11a wireless local area network (LAN) baseband part, which requires high-speed data processing. This paper describes the configuration of the SDR IEEE 802.11a software for the reconfigurable processor and its performance evaluation results. Moreover, we showed the requirements for applying the reconfigurable processor to SDR wideband mobile terminals, and confirmed that the reconfigurable processor could be applied to SDR mobile terminals by slight progresses.

In this paper we propose a new reconfigurable signal processing platform for SDR, having capability to change its processing parameters dynamically. On our proposed platform, while the wiring and processing scheme remain fixed, processing parameters and connections between processing modules together with the associated dataflow can be changed. We also demonstrate that our proposed signal processing platform has the new ability of easily composing new signal processing models dynamically, simultaneously with other tasks, and attaining high efficiency of logic usage.

To detect the theft of Java class files efficiently, we propose a concept of Java birthmarks, which are unique and native characteristics of every class file. For a pair of class files p and q, if q has the same birthmark as p's, q is suspected as a copy of p. Ideally, the birthmarks should satisfy the following properties: (a) preservation - the birthmarks should be preserved even if the original class file is tampered with, and (b) distinction - independent class files must be distinguished by completely different birthmarks. Taking (a) and (b) into account, we propose four types of birthmarks for Java class files. To show the effectiveness of the proposed birthmarks, we conduct three experiments. In the first experiment, we demonstrate that the proposed birthmarks are sufficiently robust against automatic program transformation (93.3876% of the birthmarks were preserved). The second experiment shows that the proposed birthmarks successfully distinguish non-copied files in a practical Java application (97.8005% of given class files were distinguished). In the third experiment, we exploit different Java compilers to confirm that the proposed Java birthmarks are core characteristics independent of compiler-specific issues.

This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.

According to the proliferation of ubiquitous computing, various products which contain large-size embedded software have been developed. One of most typical features of embedded software is concurrency of software and hardware factors. That is, software has connected deeply into hardware devices. The existence of various hardware make quality assurance of embedded software more difficult. In order to assure quality of embedded software more effectively, this paper discusses features of embedded software and an effective method for quality assurance for embedded software. In this paper, we first analyze a failure distribution of embedded software and discuss the effects of hardware devices on quality of embedded software. Currently, in order to reduce hardware related faults, huge effort for testing with large number of test items is required. Thus, one of the most important issues for quality assurance of embedded software is how to reduce the cost and effort of software testing. Next, focusing on hardware constraints as well as software specifications in embedded software, we propose an evaluation metrics for determinating important functions for quality of embedded software. Furthermore, by referring to the metrics, undesirable behaviors of important functions are identified as root nodes of fault tree analysis. From the result of case study applying the proposed method to actual project data, we confirmed that test items considering the property of embedded software are constructed. We also confirmed that the constructed test items are appropriate to detect hardware related faults in embedded systems.

We introduce a method, so called FC method, for maintaining software resources, such as source codes and design documents, in consumer electronics products. Because a consumer electronics product is frequently and rapidly revised, software components in such product are also revised in the same way. However, it is not so easy for software engineers to follow the revision of the product because requirements changes for the product, including the changes of its functionalities and its hardware components, are largely independent of the structure of current software resources. FC method lets software engineers to restructure software resources, especially design documents, stepwise so as to follow the requirements changes for the product easily. We report an application of this method in our company to validate it. From the application, we can confirm that the quality of software was improved about in twice, and that efficiency of development process was also improved over four times.

We have launched "Highly-Reliable Embedded Software Development" Project, held as a part of e-Society Project, supported by Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan. The aim of this project is to enable the industry to produce highly reliable and advanced software by introducing latest software technologies into embedded software development. In this paper, we introduce the overview of the projects and our activities and results so far.