Thinking process development diagram is a graphical expression from which readers can easily find not only the hierarchy of a given problem but the relationship between the problem and the solution. Although that has been developed as an idea creation support tool in the field of mechanical design, we referred to the restricted version as clamshell diagram to attempt to apply to other fields. In this paper we propose the framework for drawing the diagram of the SQL statement. The basic idea is to supply the hierarchical code fragments of a given SQL statement in the left side of the diagram and to put the meaning written in a natural language in the right. To verify the usefulness of the diagram expression, we actually drew several clamshell diagrams. For three SQL statements that are derived from the same specification, the resulting diagrams enable us to understand the difference visually.

Fractals are mathematical or natural objects that are made of parts similar to the whole in certain ways. In this paper a software reliability forecasting method of software failure is proposed based on predictability of fractal time series. The empirical failure data (three data sets of Musa's) are used to demonstrate the performance of the reliability prediction. Compared with other methods, our method is effective.

Many existing software reliability models (SRMs) are based on the assumption that fault correction activities take a negligible amount of time and resources, which is often invalid in real-life situations. Consequently, the estimated and predicted software reliability tends to be over-optimistic, which could in turn mislead management in related decision-makings. In this paper, we first make an in-depth analysis of real-life software testing process; then a Markovian SRM considering fault correction process is proposed. Parameter estimation method and software reliability prediction method are established. A numerical example is given which shows that by using the proposed model and methods, the results obtained tend to be more appropriate and realistic.

We present an attractive approach for OFDM transmission using an adaptive pre-FFT equalizer, which can select ICI reduction mode according to channel condition, and a degenerated-inverse-matrix-based channel estimator (DIME), which uses a cyclic sinc-function matrix uniquely determined by transmitted subcarriers. In addition to simulation results, the proposed system with an adaptive pre-FFT equalizer and DIME has been laboratory tested by using a software defined radio (SDR)-based test bed. The simulation and experimental results demonstrated that the system at a rate of more than 100 Mbps can provide a bit error rate of less than 10-3 for a fast multi-path fading channel that has a moving velocity of more than 200 km/h with a delay spread of 1.9 µs (a maximum delay path of 7.3 µs) in the 5-GHz band.

This paper proposes a blind image-band interference canceller that enables heterodyne receivers with only a single receiver chain to demodulate signals in any frequency band. In this paper, such a receiver is called "multimode/multiband heterodyne receiver." If multimode/multiband receivers are desired to receive signals with carrier frequency ranging from several MHz to GHz, then, such receivers are not allowed to have a narrow band RF-BPF (Radio Frequency Band Pass Filter) at the RF front end. However, although heterodyne receivers have been applied to wireless systems due to their high performance, it is known that without an RF-BPF heterodyne receivers suffer from severe image-band interference. Therefore, a blind image-band interference canceller is proposed in this paper to mitigate the image-band interference. Moreover, a novel algorithm based on the CM (Constant Modulus) criterion is proposed to carry out the cancellation. Performance of the blind image-band interference canceller is theoretically analyzed and the performance of the proposed canceller is verified by computer simulation. As a result, it is shown that the blind image-band interference canceller achieves superior performance even in the presence of strong image-band interference, for example, CIR=-40 dB. In summary, the proposed canceller makes it possible for the receiver with the single receiver chain to achieve multimode/multiband communications with high quality.

This paper proposes a dynamic capture-recapture (DCR) model to estimate not only the total number of software faults but also quantitative software reliability from observed data. Compared to conventional static capture-recapture (SCR) model and usual software reliability models (SRMs) in the past literature, the DCR model can handle dynamic behavior of software fault-detection processes and can evaluate quantitative software reliability based on capture-recapture sampling of software fault data. This is regarded as a unified modeling framework of SCR and SRM with the Bayesian estimation. Simulation experiments under some plausible testing scenarios show that our models are superior to SCR and SRMs in terms of estimation accuracy.

In this paper, we discuss software performability evaluation considering the real-time property; this is defined as the attribute that the system can complete the task within the stipulated response time limit. We assume that the software system has two operational states from the viewpoint of the end users: one is operating with the desirable performance level according to specification and the other is with degraded performance level. The dynamic software reliability growth process with performance degradation is described by the extended Markovian software reliability model with imperfect debugging. Assuming that the software system can process the multiple tasks simultaneously and that the arrival process of the tasks follows a nonhomogeneous Poisson process, we analyze the distribution of the number of tasks whose processes can be completed within the processing time limit with the infinite server queueing model. We derive several software performability measures considering the real-time property; these are given as the functions of time and the number of debugging activities. Finally, we illustrate several numerical examples of the measures to investigate the impact of consideration of the performance degradation on the system performability evaluation.

The inflection S-shaped software reliability growth model (SRGM) proposed by Ohba (1984) is one of the well- known SRGMs. This paper deals with the optimal software release problem with regard to the expected software cost under this model based on the Bayesian approach. To reflect the effect of the learning experience for the updated software system, we consider several improvement factors to adjust the values of parameters characterizing the inflection S-shaped SRGM. Appropriate prior distributions are assumed for such factors and the expected total software cost is formulated. The optimal release time is shown to be finite and uniquely determined. Because of the flexibility of prior distributions, the proposed Bayesian methods may be applied in many different situations. Numerical results are presented on the basis of the real data.

In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loops, however, there is still much room to improve the performance by exploiting the parallelism. In this paper, we, for the first time, propose a method to utilize pipelining techniques and take interconnect delays into account together so as to improve the quality of high level synthesis. The proposed method has the following two characteristics: 1) it separates the consideration of interconnect delay from computation delay, and allows concurrent data transfer and computation; 2) it belongs to modulo scheduling framework, in the sense that all iterations have identical schedules, and are initiated periodically. We evaluate our method from two different points of view. Firstly, we compare our method with an existing interconnect-aware high level synthesis that does not utilize pipelining techniques, and the experimental results show that our method can obtain about 3.4 times performance improvement on average. Secondly, we compare our method with an existing pipeline synthesis that does not consider interconnect delays, and the results show that our method can obtain about 1.5 times performance improvement on average. In addition, we also evaluate our proposed architecture and the experimental results demonstrate that it is better than existing architecture in [1].

In the OTS/CafeOBJ method, software specifications are described in CafeOBJ executable formal specification language, and verification is done by giving scripts to the CafeOBJ system. The script is called a proof score. In this study, we propose a test case generator from an OTS/CafeOBJ specification together with a proof score. Our test case generator gives test cases by analyzing the proof score. The test cases are used to test whether an implementation satisfies the specification and the property verified by the proof score. Since a proof score involves important information for verifying a property, the generated test cases are also expected to be suitable to test the property.

This paper presents a framework of multimode fully digital receiver implementation using direct RF-to-digital conversion. In this architecture the entire band including multiple RF systems is directly converted to digital by a wideband high speed ADC, and the RF systems can be easily switched by only digital signal processing with the minimum analog RF components. The digital RF front-end consists of parallel processing blocks for parallel data streams considering practical ADC's configuration. The RF signals are converted into baseband through digital IF stage and the data rates are made down by two steps of decimation. In this paper, a principle investigation into a dualmode system implementation is presented for simplicity. The circuit resource and the robustness to the spurs (spurious outputs) of an NCO (numerically controlled oscillator) in the proposed design will be presented. The proposed architecture was implemented with an FPGA on the developed prototype system and the operations were also verified.

Although software-attack detection via dynamic taint analysis (DTA) supports high coverage of program execution, it prohibitively degrades the performance of the monitored program. This letter explores the possibility of collaborative dynamic taint analysis among members of an application community (AC): instead of full monitoring for every request at every instance of the AC, each member uses DTA for some fraction of the incoming requests, thereby loosening the burden of heavyweight monitoring. Our experimental results using a test AC based on the Apache web server show that speedy detection of worm outbreaks is feasible with application communities of medium size (i.e., 250-500).

Software model checking is typically applied to components of large systems. The assumption generation is the problem of finding the least restrictive environment in which the components satisfy a given safety property. There is an algorithm to compute the environment for properties given as a regular language. In this paper, we propose a general scheme for computing the assumption even for non-regular properties, and show the uniqueness of the least restrictive assumption for any class of languages. In general, dealing with non-regular languages may fall into undecidability of problems. We also show a method to compute assumptions based on visibly pushdown automata and their finite-state abstractions.

As a variety of digital services are provided through networks, more and more efforts are made to ensure dependability of software behavior implementing services. Formal methods and tools have been considered as promising means to support dependability in complex software systems during the development. On the other hand, there have been serious doubts on practical applicability of formal methods. This paper overviews the present state of formal methods and discusses their applicability, especially focusing on two representative methods (SPIN and B Method) and their recent industrial applications. This paper also discusses applications of formal methods to dependable networked software.

Software defined radio (SDR) technology has been widely applied for its powerful universality and flexibility in the past decade. To address the issue of bandpass sampling of multiband signals, a novel and efficient method of finding the minimum valid sampling frequency is proposed. Since there are frequency deviations due to the channel effect and hardware instability in actual systems, we also consider the guard-bands between downconverted signal spectra in determining the minimum sampling frequency. In addition, the case that the spectra within the sampled bandwidth are located in inverse placement can be avoided by our proposed method, which will reduce the complexity of the succeeding digital signal process significantly. Simulation results illustrate that the proper minimum sampling frequency can be determined rapidly and accurately.

This letter presents a novel framework in high-level synthesis where hardware modules synthesized from functions in a given ANSI-C program can call the other software functions in the program. This enables high-level synthesis from C programs that contains calls to hard-to-synthesize functions, such as dynamic memory management, I/O request, or very large and complex functions. A single-thread implementation scheme is shown, whose correctness has been verified through register transfer level simulation.

Many Internet services and protocols should guarantee anonymity; for example, an electronic voting system should guarantee to prevent the disclosure of who voted for which candidate. To prove trace anonymity, which is an extension of the formulation of anonymity by Schneider and Sidiropoulos, this paper presents an inductive method based on backward anonymous simulations. We show that the existence of an image-finite backward anonymous simulation implies trace anonymity. We also demonstrate the anonymity verification of an e-voting protocol (the FOO protocol) with our backward anonymous simulation technique. When proving the trace anonymity, this paper employs a computer-assisted verification tool based on a theorem prover.

The steady approach of advanced nations toward realization of ubiquitous computing societies has given birth to rapidly growing demands for new-generation distributed computing (DC) applications. Consequently, economic and reliable construction of new-generation DC applications is currently a major issue faced by the software technology research community. What is needed is a new-generation DC software engineering technology which is at least multiple times more effective in constructing new-generation DC applications than the currently practiced technologies are. In particular, this author believes that a new-generation building-block (BB), which is much more advanced than the current-generation DC object that is a small extension of the object model embedded in languages C++, Java, and C#, is needed. Such a BB should enable systematic and economic construction of DC applications that are capable of taking critical actions with 100-microsecond-level or even 10-microsecond-level timing accuracy, fault tolerance, and security enforcement while being easily expandable and taking advantage of all sorts of network connectivity. Some directions considered worth pursuing for finding such BBs are discussed.

Programming the multiprocessor system-on-chip (MPSoC) requires partitioning the sequential reference programs onto multiple processors running in parallel. However, designers still need to partition the code manually due to the lack of automated partition techniques. To settle this issue, this paper proposes a partition exploration algorithm based on the search space smoothing techniques, and implements the proposed method using a commercial extensible processor (Xtensa LX2 processor from Tensilica Inc.). We have verified the feasibility of the algorithm by implementing the MPEG2 benchmark on the Xtensa-based two-processor system. The final experimental results indicate a performance improvement of at least 1.6 compared to the single-processor system.

The ηT pairing for supersingular elliptic curves over GF(3m) has been paid attention because of its computational efficiency. Since most computation parts of the ηT pairing are GF(3m) multiplications, it is important to improve the speed of the multiplication when implementing the ηT pairing. In this paper we investigate software implementation of GF(3m) multiplication and propose using irreducible trinomials xm+axk+b over GF(3) such that k is a multiple of w, where w is the bit length of the word of targeted CPU. We call the trinomials "reduction optimal trinomials (ROTs)." ROTs actually exist for several m's and for typical values of w = 16 and 32. We list them for extension degrees m = 97, 167, 193, 239, 317, and 487. These m's are derived from security considerations. Using ROTs, we are able to implement efficient modulo operations (reductions) for GF(3m) multiplication compared with cases in which other types of irreducible trinomials are used (e.g., trinomials with a minimum k for each m). The reason for this is that for cases using ROTs, the number of shift operations on multiple precision data is reduced to less than half compared with cases using other trinomials. Our implementation results show that programs of reduction specialized for ROTs are 20-30% faster on 32-bit CPU and approximately 40% faster on 16-bit CPU compared with programs using irreducible trinomials with general k.