This paper describes a new 0.5-µm MOS current mode Logic (MCML) circuit that operates at 1.2 V, while maintaining high-speed performance, comparable with that of bipolar current mode circuits. An MCML circuit consists of differentially operating MOS transistors and a constant current source. Its performance at low voltage is compared with that of a CMOS circuit and bipolar current mode circuits. At 1.2 V, the MCML circuit has 90% the delay time of a CMOS circuit at 3.3 V. Delay times of CML and ECL circuits are 80% and 67% of that of the MCML circuit, respectively. Power of a 0.5-µm 500-MHz MCML circuit at 1.2 V, however, is 29%, 67% and 46%, of that of CMOS at 3.3 V, CML at 1.8 V and ECL at 2.6 V, respectively. Power-delay products of 500-MHz CMOS, CML and ECL circuits (normalized by the MCML circuit power-delay product) are 3.8, 1.2 and 1.5, respectively. MCML circuits can be used to construct any logic circuits. High-speed compact circuits are feasible, because MCML circuits output complementary signals. The delay time of an MCML full adder is only 200 ps. This is three times faster than that of a 3.3-V CMOS full adder. An MCML circuit has good characteristics and is widely applicable to logic circuits, so it is a useful circuit for producing sub-GHz processors.

An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

The inherent simplicity of the LMS (Least Mean Square) Algorithm has lead to its wide usage. However, it is well known that high speed convergence and low final misadjustment cannot be realized simultaneously by the conventional LMS method. To overcome this trade-off problem, a new adaptive algorithm using Multiple ADF's (Adaptive Digital Filters) is proposed. The proposed algorithm modifies coefficients using multiple gradient vectors of the squared error, which are computed at different points on the performance surface. First, the proposed algorithm using 2 ADF's is discussed. Simulation results show that both high speed convergence and low final misadjustment can be realized. The computation time of this proposed algorithm is nearly as much as that of LMS if parallel processing techniques are used. Moreover, the proposed algorithm using more than 2 ADF's is discussed. It is understood that if more than 2 ADF's are used, further improvement in the convergence speed in not realized, but a reduction of the final misadjustment and an improvement in the stability are realized. Finally, a method which can improve the convergence property in the presence of correlated input is discussed. It is indicated that using priori knowledge and matrix transformation, the convergence property is quite improved even when a strongly correlated signal input is applied.

The selection method of the moment of inertia of the flywheel in a digital measurement system of torque-speed curve plotting for a kind of motor is presented. The selection standards of the moment of inertia and the map displaying the operating ranges of the measurement system are shown. The selection procedure of the moment of inertia is also shown.

There have been several studies related to a reduction of the amount of computational resources used by Turing machines. As consequences, Linear speed-up theorem", tape compression theorem" and reversal reduction theorem" have been obtained. In this paper, we discuss a leaf reduction theorem on alternating Turing machines. Recently, the result that one can reduce the number of leaves by a constant factor without increasing the space complexity was shown for space- and leaf-bounded alternating Turing machines. We show that for time- and leaf-bounded alternating Turing machines, the number of leaves can be reduced by a constant factor without increasing time used by the machine. Therefore, our result says that a constant factor on the leaf complexity does not affect the power of time- and leaf-bounded alternating Turing machines.