The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.

In this paper, we give a concrete example of a 10-bit video rate ADC and introduce the effect of top-down design methodology with analog-HDL from the viewpoint of utilization techniques. First, we explain that analog top-down design methodology can improve chip performance by optimizing the architecture. Next, we concretely discuss the importance of modeling and verification. Verification of the full system does not require extracting all the information for each block at the transistor level in detail. The flexible verification method that we propose can provide good and fast full chip verification. We think analog top-down disign methodology will become increasingly more important from now on because "system-on-chip" requires one chip mixed-signal system LSIs.

We propose a new network architecture nemed Holonic Network for personalized multimedia communications, which is characterized by distributed cooperative networking based on autonomous management and all-optical transport networks. We than propose autonomous routing method. Moreover, an information searching method and a route generation method with network maps, which are essential for this network, are proposed. Lastly, we evaluate the proposed network performance by theoretical analysis and system emulation.

This paper describes a millimeter-wave (MMW) transmission system over fiber-optic links applicable for high-speed mobile communications. The system design is presented considering both the MMW radio link and fiber-optic link. To prove the capability of the MMW fiber-optic link, an experimental system has been constructed. The results of in-door transmission experiments showed that this system could be capable of transmitting 118 Mbps digital signals with a BER of less than 10-6. The developed system is easily applicable to a wireless access system which can connect subscribers with a broadband optical fiber network.

Progress made in the field of high speed networking technology has led to the planning and prototyping of true high-bandwidth applications with very high throughput and low delay requirements. In this study we approach the problem of high throughput demand from the aspect of protocols and introduce the handling of error control in the application layer level as opposed to the transport layer since the eventual destination of data is the application itself. This scheme, called ACER (Application Conscious Error Recovery), is proposed and defined for bulk data transfers. A simple analytic throughput comparison of the sliding window scheme with go-back-N, and ACER is given later, Also, a prototype implementation of ACER for bulk data transfer and experimental measurement results are presented. Besides, we investigate the performance of the scheme by simulation for various network models. Finally, we present a discussion of extending the scheme to different traffic patterns and applications.

We analyzed the operation speed of the resonant tunneling logic gate, MOBILE, using a simple equivalent circuit model and varying parameters of I-V characteristics and capacitance of RTTs(resonant tunneling transistors). The switching time for large peak-to-valley(P/V)current ratios is smaller at small Vbmax(maximum bias voltage), but larger at large Vbmax than that for small P/V ratios in the case of present I-V characteristics with flat valley current. It is also demonstrated that the MOBILE operation fails if the bias voltage rises too fast, when the capacitance of the load and the driver is different due to the displacement current through the capacitance. These behaviors can be explained by considering the potential diagrams of the circuit.

Microcellular systems are suitable as personal mobile communication systems because of their high channel re-use efficiency and low transmission power. To implement a microcellular system, the antennas of base stations should be low enough, compared to the buildings around them, to reduce the interference to or from other base stations. In high-speed digital mobile radio communications, the time delay spread caused by multipath propagation is a significant factor in determining the maximum data transmission rate. In the case of a low-antenna-height microcellular system, the propagation characteristics rapidly change when the mobile terminal moves from a line-of-sight (LOS) location to a non-line-of-sight (NLOS) location. In this paper, the time dealy spread characteristics under LOS and NLOS conditions are examined using a geometrical street model which has a reflecting wall at one end of the street on which the base station is located. The RMS delay spreads are calculated using optical ray theory, taking into consideration the wedge diffraction on the street corner. If a reflecting wall exists, the RMS delay spread increases as the mobile terminal moves away from the base station under LOS conditions, or away from the street corner under NLOS conditions. The calculated results agree with the experimental results if measuring equipment noise is taken into consideration.

The problem of test generation for VLSI circuits computationally requires prohibitive costs. Parallel processing on a multiprocessor system is one of available methods in order to speedup the process for such time-consuming problems. In this paper, we analyze the performance of parallel test generation for combinational circuits. We present two types of parallel test generation systems in which the communication methods are different; vector broadcasting (VB) and fault broadcasting (FB) systems, and analyze the number of generated test vectors, the costs of test vector generation, fault simulation and communication, and the speedup of these parallel test generation systems, where the two types of communication factors; the communication cut-off factor and the communication period, are applied. We also present experimental results on the VB and FB systems implemented on a network of workstations using ISCAS'85 and ISCAS'89 benchmark circuits. The analytical and experimental results show that the total number of test vectors generated in the VB system is the same as that in the FB system, the speedup of the FB system is larger than that of the VB, and it is effective in reducing the communication cost to switch broadcasted data from vectors to faults.

Three techniques are proposed for reducing the time required for protocol processing: protocol data unit management using page management, assembly and disassembly of data packet header and contents in hardware, and rescheduling of protocol processing. These techniques were shown to be feasible by applying them to the TCP/IP over a fiber-distributed data interface network. The maximum communication throughput was 91.6 Mbps; the total throughput for 64 sessions was 89.6 Mbps, only 2% less than the maximum. These techniques will enable the development of more effcient video-on -demand systems.

The up and coming multimedia services are based on real-time high-speed networks. For efficient operation of such services, real-time and precise network management is essential. In this paper, we show that presently available MIB designs are severely inadequate to support real-time network management. We point out and analyze the management constraints and bottlenecks. The concept of quality of management of management information is introduced and its importance in practical network management is discussed. We have proposed a new MIB architecture that will raise the quality of management information to meet the requirements of managing high-speed networks and multimedia services. Experimental results from a prototype implementation of the new MIB architecture are presented.

This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.

In this paper we propose an effective ratebased virtual clock (ERVC) scheduling algorithm which is applied to the switching nodes in the connection-oriented high-speed networks. It is based on the effective rate which has a value between the average and peak transmission rates. The algorithm is simple but overcomes the defects of original virtual-clock algorithm. Performance results demonstrate the effectiveness of the ERVC algorithm in comparison with other methods.

Asynchronous Transfer Mode (ATM) is a promised bearer transmission service for high speed multimedia LAN. Recently, high speed multimedia ATM LAN products have been available. Therefore, in order to interconnect them, the multimedia backbone LAN, which has the expandable high throughput over 10Gbps, supporting multicast, multi-QoS, and many interfaces including 622 Mbps, will be widely required. In this paper, the VLSI oriented input and output buffered switch architecture is proposed as the hardware architecture for multimedia backbone switch node. This paper describes that the chip set consisting of four VLSIs, that is, the switch element, the switch access, the distributor/arbiter, and the multiplexer/demultiplexer, can realize the backbone switch core, and the main specifications required to each VLSI are derived.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.

Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.

This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.

This letter presents an efficient design method of multiplierless 2-D state-space digital filters (SSDFs) based on a genetic algorithm. The resultant multiplierless 2-D SSDFs, whose coefficients are represented as the sum of two powers-of-two terms, are attractive for high-speed operation and simple implementation. The design problem of multiplierless 2-D SSDFs described by Roesser's local state-space model is formulated subject to the constraint that the resultant filters are stable. To ensure the stability for the resultant 2-D SSDFs, a stability test routine is embedded in th design procedure.

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 µm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

The message level performance of error controls in data communication on ATM network is analyzed. Three layers, "a cell"(a unit of transmission), "a block"(a unit of error controls) and "a message"(a unit of transmission of user level) are considered. The error controls treated in this paper are GBN (Go-Back-N) and FEC+GBN. The cell loss process is assumed to be the two state Markov chain considering the cell loss process in ATM networks. Numerical results show that (1) the improvement of the message forwarding delay is saturated in some environments when the interface rate becomes high, (2) FEC is efficient when the burstiness of the cell loss process is small, the message length is large and the interface rate is high.

This paper describes ALINX (Advanced Low-voltage Interface Circuit System), a low-power and high-speed interface circuit of submicron CMOS LSI for digital information and telecommunications systems. Differential and single-ended ALINXs are low-voltage swing I/O interface circuits with less than 1.0 V swing from a 1.2 V supply. Specifically, the differential ALINX features a pair of complementary NMOS push-pull drivers operating from a 1.2 V supply, reducing power consumption compared to conventional high-speed interface circuits operating from a 5 V or 3.3 V supply. The DC power consumption is approximately 11% of ECL. We observed 622 Mbps differential transmission with 8 mW power consumption and single-ended transmission at 311 Mbps with 14 mW with a PN23 pseudo-random pattern. We also describe a noise characteristic and ALINX applications to high-speed data buses and LSI for telecommunications systems. A time/space switch LSI with 0.9 W total power consumption was fabricated by 0.5 µm CMOS process technology. This chip can use a plastic QFP.