This paper describes ALINX (Advanced Low-voltage Interface Circuit System), a low-power and high-speed interface circuit of submicron CMOS LSI for digital information and telecommunications systems. Differential and single-ended ALINXs are low-voltage swing I/O interface circuits with less than 1.0 V swing from a 1.2 V supply. Specifically, the differential ALINX features a pair of complementary NMOS push-pull drivers operating from a 1.2 V supply, reducing power consumption compared to conventional high-speed interface circuits operating from a 5 V or 3.3 V supply. The DC power consumption is approximately 11% of ECL. We observed 622 Mbps differential transmission with 8 mW power consumption and single-ended transmission at 311 Mbps with 14 mW with a PN23 pseudo-random pattern. We also describe a noise characteristic and ALINX applications to high-speed data buses and LSI for telecommunications systems. A time/space switch LSI with 0.9 W total power consumption was fabricated by 0.5 µm CMOS process technology. This chip can use a plastic QFP.

A new low-power and high-speed CMOS interface circuit is proposed in which signals are transmitted by means of impulse voltage. This mode of transmission is called impulse transmission. Although a termination resistor is used for impedance matching, the current through the output transistors and the termination resistor flows only in transient states and no current flows in stable states. The output buffer and the termination resistor dissipate power only in transient states, so their power dissipation is reduced to 30% that of conventional low-voltage-swing CMOS interface circuits at 160 MHz. The circuit was fabricated by 0.5 µm CMOS technology and was evaluated at a supply voltage of 3.3 V. Experimental results confirm low power of 4.8 mW at 160 MHz and high-speed 870 Mb/s error free point-to-point transmission.

I have examined factors for implementing a high-speed, low-power-consumption thermal head. In conventional thermal heads, a heat insulation layer is provided between the heating resistor and the radiator. I found it desirable to implement fast operation and low power consumption to lower the thermal conductivity of the heat insulation layer and to thin the heat insulation layer. I also found there is an optimum heat characteristic to the thickness of one heat insulation layer. I assumed polyimide as a material for the heat insulation layer which could materialize the hypothesis, and studied necessary items based on the thermal calculation. I manufactured a trial thermal head on the basis of this result and confirmed that our assumptions were correct. In addition, to confirm that the assumption is also ultimately correct, I fabricated a trial thermal head only consisting of a heating resistor and without a protective coat and a heat insulation layer. I confirmed that the structure with only the heating resistor exhibited excellent heat response and consumed less power necessary for heating.

Recent high-speed bipolar technologies based on SICOS (Sidewall Base Contact Structure) transistors are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. As the characteristics of the upward operated SICOS transistors are close to those of downward transistors, they can easily be applied in memory cells which have near-perfect soft-error-immunity. Newly developed process technologies for making shallow base and emitter junctions to improve circuit performance are also reviewed. Finally, complementary bipolar technology for low-power and high-speed circuits using pnp transistors, and a quasi-drift base transistor structure suitable for below 0.1 µm emitters are discussed.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

Device figure-of-merits for digital ICs are derived from analytical delay expressions for emitter-coupled logic and source-coupled FET logic inverters and are compared with the operating speeds of D-F/Fs reported in previous studies. We show that device figure-of-merits for baseband amplifiers are equivalent to those for digital ICs. The validity of device figure-of-merits are confirmed by measuring the bandwidth of the baseband amplifiers fabricated with AlGaAs/GaAs LBCTs.

This paper concerns the issue of learning strategies for problem solvers from trace data. Many works on Explanation Based Learning have proposed methods for speeding up a given problem solver (or a Prolog program) by optimizing it on some subspace of problem instances with high probability of occurrences. However, in the current paper, we discuss the issue of identifying a target strategy exactly from trace data. Learning criterion used in this paper is the identification in the limit proposed by Gold. Further, we use the tree pattern language to represent preconditions of operators, and propose a class of strategies, called decision list strategies. One of the interesting features of our learning algorithm is the coupled use of state and operator sequence information of traces. Theoretically, we show that the proposed algorithm identifies some subclass of decision list strategies in the limit with the conjectures updated in polynomial time. Further, an experimental result on N-puzzle domain is presented.

A noise cancelling sonar-ranging system based on the adaptive filtering technique, which can automatically adapt itself to the changes in environmental noise-field and improve the passive sonar-ranging/goniometric precision, was introduced by this paper. In the meantime, the software and hardware design principle of the system using high speed VLSI (Very Large Scale Integrated) DSP (Digital Signal Processing) chips, and the practical test results were also presented. In comparison with the traditional ranging system, the system not only enhanced obviously the ranging precision but also possessed some more characteristics such as simple structure, rapid operation, large data-storage volume, easy programming, high reliability and so on.

Two types of dynamic termination, latch-type and RC-type, are useful for low-power high-speed chip interconnection where the transmission line is terminated only if the signal is changed. The gate of the termination MOS in the latch-type is driven by a feedback inverter, and that in the RC-type is driven by a differentiating signal through the resistor and capacitor. The power dissipation is 13% for the latch-type, and 11% for the RC-type in a DC termination scheme, and the overshoot is 32% for the latch-type, and 16% for the RC-type in an open scheme, both at a signal amplitude of 2 V. The RC-type is superior for signal swing as low as a 1 V. On the other hand, RC termination requires large capacitance, and thus high power. Diode termination is not effective for a small swing because of the large ON voltage of diodes.

We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.

We propose a directly controlled emitter-follower circuit with a feedback type level stabilizer for low-voltage, low-power and high-speed bipolar ECL circuits. The emitter-follower circuit employs a current source structure that compensates speed and power for various supply voltage and temperature. The feedback controlled circuit with a small current source stabilizes 'High' level. At a power consumption of 1 mW/gate, the new circuit is 45% faster under the loaded condition (FO1, CL0.5 pF) and has 47% better load driving capability than conventional ECL gates.

The Distributed Queue Dual Bus protocol (DQDB) has been adopted as the metropolitan area network (MAN) standard by IEEE802.6 committee. Recently, the unfairness problem in the DQDB protocol, by which head stations benefit, has been pointed out. Although a fair bandwidth distribution among the stations is obtained by adding the so-called bandwidth balancing mechanism into the DQDB protocol (DQDB/BB), the DQDB/BB protocol leaves a portion of the available bandwidth unused, and it takes a considerable amount of time to converge to fair channel assignment. In this study, to overcome the drawbacks in DQDB and DQDB/BB, we introduce a new media access control protocol which is based on assigning each station a level according to some traffic information such as the queueing length, delay time etc. Only the station with the highest level is allowed to transmit. Through the operation of level assignment or the choice of level function, the transmission can be easily controlled in a distributed manner. This protocol is simple compared with DQDB/BB and can be implemented in the DQDB architecture. The simulation results show that the new protocol obtains not only fair throughput regardless of the distance between the stations, but also fair delay performance. In addition, the new protocol can easily provide preempty priority service through level assignment. The new protocol converges to fair distribution of the channel in the time required for only one or two round-trips. This is very fast compared with the DQDB/BB protocol.

A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p+ buried layer and a low sheet-resistance extrinsic n+ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm2. Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF2-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

B-ISDN telecommunication systems will require signal processing speeds up to 600 Mbps or more. We must therefore consider the affects of signal reflection, signal attenuation, time dalay, and so on when designing these systems. The higher the signal speed, the larger the electrical noise induced around the connector, especially in the plated through holes (PTHs) area. This paper presents the results of our investigation focused on connector mounting configurations in the signal transmission line, especially whether or not signals transmit through the PTH in a printed circuit board (PCB). How the signal reflection characteristics depend upon transmission line configurations are discussed and experimental results and simulation analyses for a transmission line system using a small miniature A-type (SMA) connector as an example are performed. It is suggested that designs for future high-speed signal transmission circuits take into account the PTH diameter and/or the PTH pitch conditions, values for which can be determined from simulation analysis.

Self-aligned InP/InGaAs heterojunction bipolar transistors (HBTs) were fabricated with emitter electrodes of 12, 22, 25, and 220 µm2 on the same wafer to investigate the influence of lateral scaling on device performance. DC characterization of these devices showed that InP/InGaAs HBTs are less subject to the emitter-size effect than GaAs-based HBTs. Common-emitter current gain β of the smallest 12-µm2 transistor was approximately 60 which is high enough for practical use. High-frequency characteristics of the transistors were almost the same in spite of the large difference in device size. Unity current-gain cutoff frequency fT of the smallest 12-µm2 transistor was as high as 163 GHz at a collector current of 2.3 mA, which ranks with the fT176 GHz achieved by the largest 220-µm2 transistor at a collector current of 45 mA. The smallest device also showed an excellent high-speed performance of fT100 GHz at submilliampere collector currents of Ic0.6 mA. The results indicate that small-lateral-dimension InP/InGaAs HBTs are applicable to high-speed ICs with low power dissipation.

Laser diodes for optical interconnections are ideally high speed, work over a wide temperature range, and are simple to bias. This paper reports high bit-rate modulation with nearly zero bias with very low threshold 1.3µm-wavelength laser diodes over a wide temperature range. At the high temperature of 80, lasing delay was 165 ps with nearly zero bias. We demonstrated 2.5 Gbit/s modulation over a wide temperature range. Eye opening was over 34% of one time slot.

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.

A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

This paper reports on the properties of thin-film thermal switches that are monolithically fabricated on high-Tc superconductive filter. Operating at a wide temperature range of 50-77 K, it was found that the switch could control the center frequency by -10 MHz with an increased insertion loss of less than 0.7 dB. In an on-off switching operation of filter characteristics using thin-film switches, power consumption was approximately 20 mW at 77 K, and the signal decay time as a switching speed was 30 ms at 76 K with a switch current of 70 mA. The decay time decreased exponentially as the switch current or the temperature setting increased.