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3541-3560hit(3578hit)

  • An Efficient One-Pass Search Algorithm for Parsing Spoken Language

    Michio OKADA  

     
    PAPER-Speech

      Vol:
    E75-A No:7
      Page(s):
    944-953

    Spoken language systems such as speech-to-speech dialog translation systems have been gaining more attention in recent years. These systems require full integration of speech recognition and natural language understanding. This paper presents an efficient parsing algorithm that integrates the search problems of speech processing and language processing. The parsing algorithm we propose here is regarded as an extension of the finite-state-network directed, one-pass search algorithm to one directed by a context-free grammar with retention of the time-synchronous procedure. The extended search algorithm is used to find approximately globally optimal sentence hypotheses; it does not have overhead which exists in, for example, hierarchical systems based on the lattice parsing approach. The computational complexity of this search algorithm is proportional to the length of the input speech. As the search process in the speech recognition can directly take account of the predictive information in the sentence parsing, this framework can be extended to sopken language systems which deal with dynamically varying constraints in dialogue situations.

  • Dynamic Path Assignment for Broadband Networks Based on Neural Computation

    Akira CHUGO  Ichiro IIDA  

     
    PAPER

      Vol:
    E75-B No:7
      Page(s):
    634-641

    This paper describes the application of a neural network to the optimal routing problem in broadband multimedia networks, where the objective is to maximize network utilization while considering the performance required for each call. In a multimedia environment, the performance required for each call is different, and an optimal path must be found whenever a call arrives. A neural network is appropriate for the computation of an optimal path, as it provides real-time solutions to difficult optimization problems. We formulated optimal routing based on the Hop field neural network model, and evaluated the basic behavior of neural networks. This evaluation confirmed the validity of the neural network formulation, which has a small computation time even if there are many nodes. This characteristic is especially suitable for a large-scale system. In addition, we performed a computer simulation of the proposed routing scheme and compared it with conventional alternate routing schemes. The results show the benefit of neural networks for the routing problem, as our scheme always balances the network load and attains high network utilization.

  • On the Frequency-Weighting Sensitivity of 2-D State-Space Digital Filters Based on the Fornasini-Marchesini Second Model

    Takao HINAMOTO  Toshiaki TAKAO  

     
    PAPER-Multidimensional Signals, Systems and Filters

      Vol:
    E75-A No:7
      Page(s):
    813-820

    Based on the Fornasini-Marchesini second local state-space (LSS) model, the coefficient sensitivities of two-dimensional (2-D) digital filters are analyzed in conjunction with frequency weighting functions. The overall sensitivity called the frequency-weighting sensitivity is then evaluated using the 2-D generalized Gramians that are newly introduced for the Fornasini-Marchesini second LSS model. Next, the 2-D filter structures that minimize the frequency-weighting sensitivity are synthesized for two cases of no constraint and scaling constraints on the state variables. Finally, an example is given to illustrate the utility of the proposed technique.

  • Runlength-Limited Codes which Turn Peak-Shift Errors into Unidirectional Byte Errors

    Yuichi SAITOH  Hideki IMAI  

     
    LETTER

      Vol:
    E75-A No:7
      Page(s):
    898-900

    In this letter, we consider a magnetic or optical recording system employing a concatenated code that consists of a runlength-limited (d, k) block code as an inner code and a byte-error-correcting code as an outer code. (d, k) means that any two consecutive ones in the code bit stream are separated by at least d zeros and by at most k zeros. The minimum separation d and the maximum separation k are imposed in order to reduce intersymbol interference and extract clock control from the received bit stream, respectively. This letter recommends to use as the outer code a unidirectional-byte-error-correcting code instead of an ordinary byte-error-correcting code. If we devise the mapping of the code symbols of the outer code onto the codewords of the inner code, we may improve the error performance. Examples of the mappings are described.

  • Selection Method of a Flywheel for Digital Measurement System of Torque-Speed Curve

    Kohji HIGUCHI  

     
    LETTER-Instrumentation and Control

      Vol:
    E75-C No:6
      Page(s):
    744-746

    The selection method of the moment of inertia of the flywheel in a digital measurement system of torque-speed curve plotting for a kind of motor is presented. The selection standards of the moment of inertia and the map displaying the operating ranges of the measurement system are shown. The selection procedure of the moment of inertia is also shown.

  • Coherent Subcarrier Multiplexed System with Distributing Local Oscillator in Local Loop

    Tomoaki OHTSUKI  Hiroyuki YASHIMA  Iwao SASASE  Shinsaku MORI  

     
    PAPER

      Vol:
    E75-B No:6
      Page(s):
    499-505

    We propose the coherent subcarrier multiplexed (SCM) system with distributing local oscillator (LO) in local loop. The proposed system can realize multichannel transmission with one optical carrier by using the SCM technique and has no need to have LO at each station. Therefore the proposed system becomes cost-effective. The proposed SCM system uses bandpass filter to select a specific channel. We analyze CNR of the system with frequency-shift keying (FSK) in a multioctave configuration. First, the general expression of CNR is derived and is shown for the following parameters such as the number of channels, the position of station on the loop, and the number of stations on the loop. Second, optimal phase modulation (PM) index is derived, and the optimal CNR, minimum required power of lasers, and maximum number of stations that the proposed system can serve are shown by using it. Moreover CNR of the proposed system is compared with that of the system having LO at each station in local loop. It is shown that the proposed system can obtain good performance at the expense of slight increase of the output power of only two lasers at the central station. Therefore the proposed system is cost-effective and practical.

  • Realization of Immittance Floatator Using Nullors

    Masami HIGASHIMURA  Yutaka FUKUI  

     
    PAPER-Analog-IC Circuit Analysis and Synthesis

      Vol:
    E75-A No:6
      Page(s):
    644-649

    This paper treats the synthesis of immittance floatator using nullors. Eight sets of circuit equations for realizing immittance floatators and their nullor (nullator-norator) representations are given. By replacing nullors with active elements such as biporlar junction transistors (BJTs), current conveyors (CCIIs), operational amplifiers (OAs) and operational transconductance amplifiers (OTAs), the immittance floatators can be derived. The development is important because it enables one to convert the present wealth of knowledge concerning grounded immittance simulation networks into floating immittance simulation networks. Using immittance floatators, we can obtain not only the floating form of 1-port but also that of 2-port networks. Novel circuits use solely minus-type norators. Using one-type (minus- or plus-type) norators greatly simplifies the simulation circuit. In the case of an immittance floatator using CCIIs as the active elements, the effects of nonideal CCIIs and sensitivities are given. Many circuits can be systematically derived using nullor technique.

  • Scheduling a Task Graph onto a Message Passing Multiprocessor System

    Tsuyoshi KAWAGUCHI  

     
    PAPER-Combinational/Numerical/Graphic Algorithms

      Vol:
    E75-A No:6
      Page(s):
    670-677

    In this paper we study the problem of scheduling parallel program modules onto an MPS (message passing multiprocessor system) so as to minimize the total execution time. Each node in the interconnection network of the MPS has buffers at its input ports to store messages waiting for the transmission. An algorithm for finding a route which minimizes the communication delay of a message to be sent between a processor-pair is first given. Next, we present heuristic algorithms for scheduling program modules onto the MPS. These algorithms use the above routing algorithm. The performances of the proposed algorithms are estimated by using simulation experiments.

  • On Translating a Set of C-Oriented Faces in Three Dimensions

    Xue-Hou TAN  Tomio HIRATA  Yasuyoshi INAGAKI  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E75-D No:3
      Page(s):
    258-264

    Recently much attention has been devoted to the problem of translating a set of geometrical objects in a given direction, one at a time, without allowing collisions between the objects. This paper studies the translation problem in three dimensions on a set of c-oriented faces", that is, the faces whose bounding edges have a constant number c of orientations. We solve the problem in O(N log2 NK) time and O(N log N) space, where N is the total number of edges of the faces and K is the number of edge intersections in the projection plane. As an intermediate step, we also solve a problem related to ray-shooting. The algorithm for translating c-oriented faces finds uses in computer graphic systems.

  • Image Compression and Regeneration by Nonlinear Associative Silicon Retina

    Mamoru TANAKA  Yoshinori NAKAMURA  Munemitsu IKEGAMI  Kikufumi KANDA  Taizou HATTORI  Yasutami CHIGUSA  Hikaru MIZUTANI  

     
    PAPER-Neural Systems

      Vol:
    E75-A No:5
      Page(s):
    586-594

    Threre are two types of nonlinear associative silicon retinas. One is a sparse Hopfield type neural network which is called a H-type retina and the other is its dual network which is called a DH-type retina. The input information sequences of H-type and HD-type retinas are given by nodes and links as voltages and currents respectively. The error correcting capacity (minimum basin of attraction) of H-type and DH-type retinas is decided by the minimum numbers of links of cutset and loop respectively. The operation principle of the regeneration is based on the voltage or current distribution of the neural field. The most important nonlinear operation in the retinas is a dynamic quantization to decide the binary value of each neuron output from the neighbor value. Also, the edge is emphasized by a line-process. The rates of compression of H-type and DH-type retinas used in the simulation are 1/8 and (2/3) (1/8) respectively, where 2/3 and 1/8 mean rates of the structural and binarizational compression respectively. We could have interesting and significant simulation results enough to make a chip.

  • The Self-Validating Numerical Method--A New Tool for Computer Assisted Proofs of Nonlinear Problems--

    Shin'ichi OISHI  

     
    INVITED SURVEY PAPER-Nonlinear Systems

      Vol:
    E75-A No:5
      Page(s):
    595-612

    The purpose of the present paper is to review a state of the art of nonlinear analysis with the self-validating numerical method. The self-validating numerics based method provides a tool for performing computer assisted proofs of nonlinear problems by taking the effect of rounding errors in numerical computations rigorously into account. First, Kantorovich's approach of a posteriori error estimation method is surveyed, which is based on his convergence theorem of Newton's method. Then, Urabe's approach for computer assisted existence proofs is likewise discussed. Based on his convergence theorem of the simplified Newton method, he treated practical nonlinear differential equations such as the Van der Pol equation ahd the Duffing equation, and proved the existence of their periodic and quasi-periodic solutions by the self-validating numerics. An approach of the author for generalization and abstraction of Urabe's method are also discribed to more general funcional equations. Furthermore, methods for rigorous estimation of rounding errors are surveyed. Interval analytic methods are discussed. Then an approach of the author which uses rational arithmetic is reviewed. Finally, approaches for computer assisted proofs of nonlinear problems are surveyed, which are based on the self-validating numerics.

  • A Self-Consistent Linear Theory of Gyrotrons

    Kenichi HAYASHI  Tohru SUGAWARA  

     
    PAPER-Microwave and Millimeter Wave Technology

      Vol:
    E75-C No:5
      Page(s):
    610-616

    A new set of self-consistent linear equations is presented for the analysis of the startup characteristics of gyrotron oscillators with an open cavity consisting of weakly irregular waveguides. Numerical results on frequency detuning and oscillation starting current for a whispering-gallery-mode gyrotron are described in which these equations were utilized. Experiments for making a check on the effectiveness of the derived equations showed that they well express the operation of gyrotrons in comparison with the linear theory using an empty cavity field as the wave field.

  • New Classes of Majority-Logic Decodable Double Error Correcting Codes for Computer Memories

    Toshio HORIGUCHI  

     
    PAPER-Fault Tolerant Computing

      Vol:
    E75-D No:3
      Page(s):
    325-333

    A new class of (m23m1,m2) 1-step majority-logic decodable double error correcting codes (1-step DEC codes) is described, where m is an odd integer. Combining this code with properly constructed (m1k1,k1) and (m,k2) 1-step DEC codes, a (m23(mk1)1,m23k1) 1-step DEC code and a (m23(mk2)1,m2) 2-step majority-logic decodable DEC code (2-step DEC code) are obtained, respectively. Considering computer memory applications, some practical 1 -and 2-step DEC codes with data-bit lengths of 24, 32, 64 and 72 are obtained by shortening the new codes, and are compared to existing majority-logic decodable DEC codes. It is shown that, for given data-bit lengths, new 2-step DEC codes have much better code rates than self-orthogonal DEC codes but slightly worse code rates than existing 2-step majority-logic decodable cyclic DEC codes (2-step cyclic DEC codes). However, parallel decoders of new 2-step DEC codes are much simpler than those of exisiting 2-step cyclic DEC codes, and are nearly as simple as those of 1-step DEC codes.

  • Separating Capabilities of Three Layer Neural Networks

    Ryuzo TAKIYAMA  

     
    SURVEY PAPER-Neural Systems

      Vol:
    E75-A No:5
      Page(s):
    561-567

    This paper reviews the capability of the three layer neural network (TLNN) with one output neuron. The input set is restricted to a finite subset S of En, and the TLNN implements a function F such as F : S I={1, -1}, i,e., F is a dichotomy of S. How many functions (dichotomies) can it compute by appropriately adjusting parameters in the TLNN? Brief historical review, some theorems on the subject obtained so far, and related topics are presented. Several open problems are also included.

  • Overview of Visual Telecommunication Activities in Japan

    Takahiko KAMAE  

     
    INVITED PAPER

      Vol:
    E75-B No:5
      Page(s):
    313-318

    The states-of-the-art in visual communication in Japan are described. First the status of networks, which is a basis for offering visual communication service, is outlined. Visual communication service being developed on the basis of ISDN is described. The future service can be represented by NTT's service vision VI&P. Visual communication technologies and services being studied are surveyed.

  • A Model for the Development of the Spatial Structure of Retinotopic Maps and Orientation Columns

    Klaus OBERMAYER  Helge RITTER  Klaus J. SCHULTEN  

     
    INVITED PAPER

      Vol:
    E75-A No:5
      Page(s):
    537-545

    Topographic maps begin to be recognized as one of the major computational structures underlying neural computation in the brain. They provide dimension-reducing projections between feature spaces that seem to be established and maintained under the participation of selforganizing, adaptive processes. In this contribution, we investigate how well the structure of such maps can be replicated by simple adaptive processes of the kind proposed by Kohonen. We will particularly address the important issue, how the dimensionality of the input space affects the spatial organization of the resulting map.

  • A Testable Design of Sequential Circuits under Highly Observable Condition

    WEN Xiaoqing  Kozo KINOSHITA  

     
    PAPER-Fault Tolerant Computing

      Vol:
    E75-D No:3
      Page(s):
    334-341

    The outputs of all gates in a circuit are assumed to be observable unber the highly observable condition, which is mainly based on the use of E-beam testers. When using the E-beam tester, it is desirable that the test set for a circuit is small and the test vectors in the test set can be applied in a successive and repetitive manner. For a combinational circuit, these requirements can be satisfied by modifying the circuit into a k-UCP circuit, which needs only a small number of tests for diagnosis. For a sequential circuit, however, even if the combinational portion has been modified into a k-UCP circuit, it is impossible that the test vectors for the combinational portion can always be applied in a successive and repetitive manner because of the existence of feedback loops. To solve this problem, the concept of k-UCP scan circuits is proposed in this paper. It is shown that the test vectors for the combinational portion in a k-UCP scan circuit can be applied in a successive and repetitive manner through a specially constructed scan-path. An efficient method of modifying a sequential circuit into a k-UCP scan circuit is also presented.

  • Analysis of Fault Tolerance of Reconfigurable Arrays Using Spare Processors

    Kazuo SUGIHARA  Tohru KIKUNO  

     
    PAPER-Fault Tolerant Computing

      Vol:
    E75-D No:3
      Page(s):
    315-324

    This paper addresses fault tolerance of a processor array that is reconfigurable by replacing faulty processors with spare processors. The fault tolerance of such a reconfigurable array depends on not only an algorithm for spare processor assignment but also the folloving factor of an organization of spare processors in the reconfigurable array: the number of spare processors; the number of processors that can be replaced by each spare processor; and how spare processors are connected with processors. We discuss a relationship between fault tolerance of reconfigurable arrays and their organizations of spare processors in terms of the smallest size of fatal sets and the reliability function. The smallest size of fatal sets is the smallest number of faulty processors for which the reconfigurable array cannot be failure-free as a processor array system no matter what reconfiguration is used. The reliability function is a function of time t whose value is the probability that the reconfigurable array is failure-free as a processor array system by time t when the best possible reconfiguration is used. First, we show that the larger smallest size of fatal sets a reconfigurable array has, the larger reliability function it has by some time. It suggests that it is important to maximize the smallest size of fatal sets in orer to improve the reliability function as well. Second, we present the best possible smallest size of fatal sets for nn reconfigurable arrays using 2n spare processor each of which is connected with n processors. Third, we show that the nn reconfigurable array previously presented in a literature achieves the best smallest size of fatal sets. That is, it is optimum with respect to the smallest size of fatal sets. Fourth, we present an uppr bound of the reliability function of the optimum nn reconfigurable array using 2n spare processors.

  • A Simulation Model of Hyperthermia by RF Capacitive Heating

    Yasutomo OHGUCHI  Naoki WATANABE  Yoshiro NIITSU  Osamu DOI  Ken KODAMA  

     
    PAPER-Medical Electronics and Medical Information

      Vol:
    E75-D No:2
      Page(s):
    219-250

    A new model for a computer simulation of RF capacitive type hyperthermia has been developed by taking account of the following points. Blood flow is usually determined by many physiological parameters, but is regarded as a function of only blood temperature under some conditions. The temperature dependence of blood flow of tumors and normal tissues is assumed by referring the data obtained by Song et al. and Tanaka. The blood temperature which is elevated by externally applied power significantly affects temperatures of the body and the tumors. The transport of heat from the body surface is studied by considering air convection. These points are examined by experiments on a computer with simple phantom models and real patients. The results of simulation on the patient have shown a good agreement with clinical inspection based on CT images and a temperature of the stomach.

  • Delta Domain Lyapunov Matrix Equation--A Link between Continuous and Discrete Equations--

    Takehiro MORI  Inge TROCH  

     
    LETTER-Control and Computing

      Vol:
    E75-A No:3
      Page(s):
    451-454

    It has been recognized that there exist some disparities between properties of continuous control systems and those of discrete ones which are obtained from their continuous counterparts by use of a sampler and zero order hold. This still remains true even if the sampling rate becomes fast enough and sometimes causes unfavorable effects in control systems design. To reconcile with this conflict, use of delta operator has been proposed in place of z-operator recently. This note formulates a delta domain Lyapunov matrix equation and shows that the equation actually mediates the discrete Lyapunov equation and its continuous counterpart.

3541-3560hit(3578hit)