Space-time tradeoff is a very fundamental issue to design a fault-tolerant real-time (called responsive) system. Routing a message in large computer networks is efficient when each node knows the full topology of the whole network. However, in the hierarchical routing schemes, no node knows the full topology. In this paper, a tradeoff between an optimality of path length (message delay: time) and the amount of topology information (routing table size: space) in each node is presented. The schemes to be analyzed include K-scheme (by Kamoun and Kleinrock), G-scheme (by Garcia and Shacham), and I-scheme (by authors). The analysis is performed by simulation experiments. The results show that, with respect to average path length, I-scheme is superior to both K-scheme and G-scheme, and that K-scheme is better than G-scheme. Additionally, an average path length in I-scheme is about 20% longer than the optimal path length. On the other hand, for the routing table size, three schemes are ranked in reverse direction. However, with respect to the order of size of routing table, the schemes have the same complexity O (log n) where n is the number of nodes in a network.

This paper proposes a reconfigurable parallel processor based on a two-dimensional linear celular automaton model. The processor based on the model can be reconfigured quickly by utilizing the characteristics of the automaton used for its model. Moreover, the processor has short data path length between processing elements compared with the length of the processor based on one-dimensional linear cellular automaton model which has been already discussed. The processing elements of the processor based on the two-dimensional linear cellular automaton model are regarded as cells and the operational states of the processor are treated as the states of the automaton. When faults are detected, the processor can be reconfigured by changing its state under the state transition function of the processor determined by the weighting function of the automaton model. The processor can be reconfigured within a clock period required for making a state transition. This processor is extremely effective for real-time data processing systems required high reliability.

Queueing problems are investigated for very wide classes of input traffic and service time models to obtain good loss probability and waiting time probability approximation. The proposed approximation is based on the fundamental recursion formula and the Chernoff bound technique, both of which requires no particular assumption for the stochastic nature of input traffic and service time, such as renewal or markovian properties. The only essential assumption is stationarity. We see that the accuracy of the obtained approximation is confirmed by comparison with computer simulation. There are a number of advantages of the proposed method of approximation when we apply it to network capacity design or path accommodation design problems. First, the proposed method has the advantage of applying to multi-media traffic. In the ATM network, a variety of bursty or non-bursty cell traffic exist and are superposed, so some unified analysis methodology is required without depending each traffic's characteristics. Since our method assumes only the stationarity of input and service process, it is applicable to arbitrary types of cell streams. Further, this approach can be used for the unexpected future traffic models. The second advantage in application is that the proposed probability approximation requires only small amount of computational complexity. Because of the use of the Chernoff bound technique, the convolution of every traffic's probability density fnuction is replaced by the product of probability generating functions. Hence, the proposed method provides a fast algorithm for, say, the call admission control problem. Third, it has the advantage of accuracy. In this paper, we applied the approxmation to the cases of homogeneous CBR traffic, non-homogeneous CBR traffic, M/D/1, AR(1)/D/1, M/M/1 and D/M/1. In all cases, the approximating values have enough accuracy for the exact values or computer simulation results from low traffic load to high load. Moreover, in all cases of the numerical comparison, our approximations are upper bounds of the real values. This is very important for the sake of conservative network design.

A new automated main distributing frame (AMDF) system is developed that reduces operating costs in metallic-cable main distributing frames (MDFs) used for communication networks. In this AMDF system, a robot inserts connecting-pins into the crosspoint holes of matrix-boards. This process allows jumpering to be completed within three minutes and the route-setting for line testing within one minute. The AMDF system provides approximately 2,100 office equipment cable-terminals. Parallel installation of several AMDF systems allows larger MDF systems to be constructed. This system reduces costs and achieves high reliability through three new technologies: high-density matrix-board, precision pin-handling, and a highly reliable system control. Test results for a prototype AMDF system confirm their effectiveness.

A soft-decision decoding algorithm for binary linear block codes is proposed. This algorithm seeks to minimize the block error probability. With careful examinations of the first hard-decision decoded results, the candidate codewords are efficiently searched for. Thus, we can reduce the decoding complexity (the number of hard-decision decodings) and lower the block error probability. Computer simulation results are presented for the (23, 12) Golay code. They show that the decoding complexity is considerably reduced and the block error probability is close to that of the maximum likelihood decoder.

The design of a high speed self-routing network switch module is described. Clock distribution and timing design to achieve high-speed operation are considered. A 88-port self-routing Benes network switch prototype on multi-chip module is fabricated using 44-port space division switch LSIs. The switch module achieves a maximum measured clock frequency of 750MHz under switching operation. Resultant total throughput of the switch module is 12Gbit/s.

Radar imaging technique is one of the most powerful tool for underground detection. However, performance of conventional methods is not sufficiently high when the observational direction or the aperture size is restricted. In the present paper, an image reconstruction method based on a model fitting with nonlinear least-squares has been developed, which is applicable to arbitrarily arranged arrays. Reconstruction is executed on the assumption that targets consist of discrete point scatterers embedded in a homogeneous medium. Model fitting is iterated as the number of point target in the assumed model is increased, until the residual in fitting becomes unchanged or small enough. A penalty function is used in nonlinear least-squares to make the algorithm stable. Fundamental characteristics of the method revealed with computer simulation are described. This method focuses a much sharper image than that obtained by the conventional aperture synthesis technique.

This paper presents a linear time optimal algorithm to a channel pin assignment problem for hierarchical building-block layout design. The channel pin assignment problem is to determine positions of the pins of nets on the top and the bottom sides of a channel, which are partitioned into several intervals, and the pins are permutable within their associated intervals. The channel pin assignment problem has been shown NP-hard in general. We present a linear time optimal algorithm for an important special case of the problem, in which there is at most one pin of a net within each interval in the channel. The proposed algorithm is optimal in a sense that it can minimize both the channel density and the total wire length of the channel. We also disscuss how to apply our algorithm to the pin assignment in the L-shaped and staircase channels. Experimental results indicate that substantial reduction in both channel density and estimated total wire length can be obtained by permuting pins in each interval. Combining the proposed algorithm with a conventional channel router, results of channel routing also achieve large amount of reduction of the number of tracks, total wire length, and the number of vias.

There have been several studies related to a reduction of the amount of computational resources used by Turing machines. As consequences, linear speed-up theorem" tape compression theorem", and reversal reduction theorem" have been obtained. In this paper, we consider reversal- and leaf-bounded alternating Turing machines, and then show that the number of leaves can be reduced by a constant factor without increasing the number of reversals. Thus our results say that a constant factor on the leaf complexity does not affect the power of reversal- and leaf-bounded alternating Turing machines

An analysis of wave guidance by surface-relief grating waveguides is presented for the case of oblique propagation. This analysis is based on the first-order differential equations expressing the coupling of the space harmonics and an improved differential method is applied to solve the equations in the grating region with arbitrary profile. The propagation constants are calculated for isotropic grating waveguids with sinusoidal profile and the calculated results indicate that the accurate solutions can be obtained by increasing the number of expansion terms and the number of segments. Moreover, this method is extended to the case of the analysis of obliquely propagating waves and it is shown that peculiar leaky waves and stop bands appear owing to the coupling between TE and TM waves.

The paper presents the improvement of out new approach to optimize the process parameter variation, device heat and wire parasitics for analog LSI design by explicitly incorporating various performance estimations into objective functions for placement and routing. To minimize these objective functions, the placement by the simulated annealing method, and maze routing are effectively modified with the perfomance estimation. The improvement results in the excellent performance driven layout for the large size of analog LSIs.

Evolution programs have been shown to be very useful in a variety of search and optimization problems, however, until now, there has been little attempt to apply evolution programs to channel routing problem. In this paper, we present an exolution program and identify the key points which are essential to successfully applying evolution programs to channel routing problem. We also indicate how integrating heuristic information related to the problem under consideration helps in convergence on final solutions and illustrate the validity of out approach by providing experimental results obtained for the benchmark tests. compared with the optimal solutions.

The scattering of electromagnetic waves by a dielectric grating with planar slanted-fringe is analyzed using the improved Fourier series expansion method. In the analysis, the slanted grating region is divided into layers to make an assembly of stratified thin modulated index layers. This method can be applied to a wide range of periodic structures and is especially effective in the case of planar slanted grating, because the electromagnetic fields in the each layer can easily be obtained by shifting the solution in the first layer. In this paper, the numerical results are given for grating with rectangular and sinusoidal dielectric profiles, and for TM and TE cases of arbitrary incident angle. The diffraction efficiencies obtained by the presented method are compared with the results by the coupled-wave approach; the influences of the slant angle on the diffraction efficiencies at the Wood's anomaly and at the coupling resonance frequency are also discussed.

For each two positive integers r, s, let [1DCM(r)-Time(ns)] ([1NCM(r)-Time(ns)]) and [1DCM(r)-Space(ns)] ([1NCM(r)-Space(ns)]) be the classes of languages accepted in time ns and in space ns, respectively, by one-way deterministic (nondeterministic) r-counter machines. We show that for each X{D, N}, [1XCM(r)-Time(ns)][1XCM(r+1)-Time(ns)] and [1XCM(r)-Space(ns)][1XCM(r+1)-Space(ns)]. We also investigate the relationships between one-way multicounter machines and cooperating systems of one-way finite automata. In particular, it is shown that one-way (one-) counter machines and cooperating systems of two one-way finite automata are equivalent in accepting power.

The inverse problem we consider in this paper seeks, based on the equivalent source method, to determine the shape of perfectly conducting cylinders from the scattered farfield data obtained by using several incident waves. When incident waves of different frequencies are used, the shape of the scatterer can be reconstructed by employing only a few number of observation points. In the reconstruction problem, to determine the shape of the scatterer, the conjugate gradients method is applied. The general approach is applicable to cylindrical scatterers of arbitrary shape. Results of numerical simulations are presented to support the suggested approach.

This paper discusses methods and numerical simulations of one and two dimensional profilings for an arbitrary convex conducting target using the electromagnetic backscattering. The inversions for profile reconstructions are based upon the modified extended physical optics method (EPO). The modified EPO method assumes the modified physical optics current properly over the entire surface of conducting scatterers. First, the cross sectional area along a line of sight is reconstructed by performing iteratively the Fourier transform of the backscattering field in the frequency domain. Second, the two dimensional profile is reconstructed by synthesizing the above one dimensional results for several incident angles. Numerical simulation results of the target profiling are shown for spheroids and cone-spheroid.

The characteristics of an open-boundary Cherenkov laser for an electromagnetic wave with a continuous frequency spectrum are numerically analyzed. A given power spectral density for the input wave is found to get concentrated around the frequency where the spatial growth rate is maximum, as it grows along the electron beam. In addition, the frequency for the maximum growth rate is found to shift gradually to higher values. Furthermore, by gradually increasing the permittivity of the dielectric waveguide along it, we can always get the maximum power spectral density at the frequency where the spatial growth rate initially becomes maximum at the input.

As RAMs become dense, their reliability reduces because of complex interactions between memory cells and soft errors due to alpha particle radiations. In order to rectify this problem, RAM manufacturers have started incorporating on-chip (built-in) ECC. In order to minimize the area overhead of on-chip ECC, the same technology is used for implementing the check bits and the information bits. Thus the check bits are exposed to the same failure modes as the information bits. Furthermore, faults in the check bits will manifest as uncorrectable multiple errors when a soft error occurs. Therefore it is important to test the check bits for all failure modes expected of other cells. In this paper, we formulate the problem of testing RAMs with on-chip ECC capability. We than derive necessary and sufficient conditions for testing the check bits for arbitrary and adjacent neighborhood pattern sensitive faults. We also provide an efficient solution to test a memory array of N bits (including check bits) for 5-cell neighborhood pattern sensitive faults in O (N) reads and writes, with the check bits also tested for the same fault classes as the information bits.

In this paper we present a method to generate test sequences for stuck-at faults in sequential circuits which have distinguishing sequences. Since the circuit may have no distinguishing sequence, we use two design techniques for circuits which have distinguishing sequences. One is at state transition level and the other is at gate level. In our proposed method complete test sequence can be generated. The sequence consists of test vectors for the combinational part of the circuit, distinguishing sequences and transition sequences. The test vectors, which are generated by a combinational test generator, cause faulty staes or faulty output responses for a fault, and disinguishing sequences identify the differences between faulty states and fault free states. Transition sequences are necessary to make the state in the combinational vectors. And the distinguishing sequence and the transition sequence are used in the initializing sequence. Some techniques for shortening the test sequence is also proposed. The basic ideas of the techniques are to use a short initializing sequence and to find the order in concatenating sequences. But fault simulation is conducted so as not to miss any faults. The initializing sequence is obtained by using a distinguishing sequence. The efficiency of our method is shown in the experimental results for benchmark circuits.

Test pattern generation is getting much harder as the circuit size becomes larger. One problem is that it tends to take much time and another one is that it is difficult to detect redundant faults. Aiming to cope with these problem, an enhanced unique sensitization technique is proposed in this paper. This powerful global implication reduces the number of backtracks with reasonable computational time. And a fast test pattern generator featuring this unique sensitization demonstrates its performance using large benchmark circuits with over ten thousands of gates. It takes only a minute to detect all testable faults and to identify all redundant faults of 20,000 gates circuit on a workstation.