This letter proposes an efficient lossless compression method for high dynamic range (HDR) images in OpenEXR format. The proposed method transforms an HDR image to an indexed image and packs the histogram of the indexed image. Finally the packed image is losslessly compressed by using any existing lossless compression algorithm such as JPEG 2000. Experimental results show that the proposed method reduces the bit rate of compressed OpenEXR images compared with equipped lossless compression methods of OpenEXR format.

The Real-time VLBI Correlator (RVC) is a new type processor for the Very-Long-Baseline Interferometry (VLBI). This correlator was primarily designed for supporting the VLBI Space Observatory Programme (VSOP). Two particular techniques, the fringe rotator after correlation and the lag-time extension technique, are newly developed for the RVC. The correlation circuit size of VLBI correlator is reduced to half by introducing the new fringe rotator, and it makes possible to realize a large delay window being essential in finding a cross correlation in real-time. The delay window can be changed flexibly with the lag-time extension technique, and its technique is useful to detect the fringe peak in a VSOP observation. The new correlator was installed at the Usuda Deep Space Center in Japan, and is used in VSOP and other domestic VLBI observations. In this paper, the key features of the Real-time VLBI Correlator (RVC) focusing on these advanced techniques are presented, and the results of its performance test are shown.

A new reference voltage generator for megabit DRAMs is proposed. The supply voltage dependence of the generator is successfully suppressed in comparison with the conventional reference voltage circuit. It is shown that the Vcc Margin of DRAM operation can be noticeably improved by using this generator.

Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient “glasses-shaped” inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.

We explore the maximum total number of edge crossings and the maximum geometric thickness of the Euclidean minimum-weight (k, ℓ)-tight graph on a planar point set P. In this paper, we show that (10/7－ε)|P| and (11/6－ε)|P| are lower bounds for the maximum total number of edge crossings for any ε ＞ 0 in cases (k,ℓ)=(2,3) and (2,2), respectively. We also show that the lower bound for the maximum geometric thickness is 3 for both cases. In the proofs, we apply the method of arranging isomorphic units regularly. While the method is developed for the proof in case (k,ℓ)=(2,3), it also works for different ℓ.