In the future satellite broadcasting system in 21GHz band, the rainfall attenuation is a most significant problem. To solve this problem, the hierarchical transmission systems have been studied. This paper analyzes the performance of the hierarchical modulation scheme from the view point of power assignment in the presence of the rainfall attenuation. This paper shows an optimum power assignment ratio to maximize the spectral efficiency and the signal-to-noise ratio of received image, and these optimum ratio is varied with the measure of system performance.

Error-correction techniques can be used to reduce the required carrier-to-noise ratio (C/N) in digital satellite news gathering (SNG) systems. The required e.i.r.p. of a digital SNG terminal is smaller than that of conventional analog SNG RF terminals. In this paper, a Ku-band portable SNG RF terminal using a flat antenna is proposed to make the best use of these digital systems. This portable terminal uses 16 planar microstrip subarray antennas, each with a solid-state power amplifier (SSPA) mounted on its backside. The proposed RF terminal is distinctly different from a conventional RF terminal with a parabolic antenna in two ways; it is portable and it has electronic tracking capability. Electronic antenna tracking reduces the terminal setup time because precise alignment of the antenna with the satellite is not required. This paper first describes the system concept and discusses the design concept. Secondly, it then explains phase shifters and feedback loops for electronic tracking. The tracking performance of a feedback system using four subarrays is also presented with some comparisons between theoretical and measured results. Experimental results for the low side-lobe flat antenna and the SSPAs are then presented. These are the most important components of the system. The flat antenna meets the design objectives specified by ITU-R Recommendations. By orthogonally exciting the rectangular patch antenna, the flat antenna is capable of operating dual polarizations and dual frequencies (transmit/vertical polarization: 14GHz; receive/horizontal polarization: 12GHz). The SSPAs have an efficiency of 21% and an output power of 5W.

A queueing model suitable for multimedia packets with Poisson and batch Poisson arrivals is studied. In the queueing model, priority is given to the packets with batch Poisson arrival, and the packets with Poisson arrival, accumulated in a buffer, are routed by utilizing intervals of the packets with priority. The queueing performance of the proposed model is evaluated by the mean system delay. We also consider the effect of batch size and the ratio of the traffic with batch Poisson arrival and the one with Poisson arrival on the mean system delay. It is found that the proposed queueing model is useful to reduce the mean system delay of the packets with Poisson arrival, while maintaining the means system delay of the packets with batch Poisson arrival.

We are studying a novel concept of the on-line hospital system using a virtual environment called Hyper Hospital," the Hyper Hospital" is a medical care system which is constructed in a distributed manner to the electronic information network using virtual reality (VR) as a human interface. In the present report, we studied the physiological and psychological responses of healthy subjects induced by the usage of the VR in terms of fatigue. Twenty healthy young male subjects were exposed to the virtual reality system and they performed some psychological tasks with a virtual nurse for 30 minutes. Several parameters of physiological, psychological, and subjective fatigue were measured. None of the physiological or psychological parameters such as urinary catecholamine release, ECG, etc. showed significant fatigue induced by our VR system. However, by using a standard questionnaire, some kinds of subjective fatigue were noted and they were thought to be indicating a direction of improvement for our VR system.

A novel low-power dissipation and high-speed converter-control-IC has been developed for the transmitting amplifier in digital portable telephones. The IC consists mainly of CMOS devices to reduce the bias current. To improve circuit speed, bipolar transistors are used in the output stage of the operational amplifier and in the current sources of the oscillator because they have a larger current capability and smaller parasitic capacitance than CMOS devices. The IC has one-fifth the bias current of a conventional control circuit consisting of discrete devices, and it can operate up to a switching frequency of 3MHz. The small bias current increases converter efficiency, and the high switching frequency reduces converter size. Using this IC, converter loss is 17% less than that with a conventional control circuit.

Throughout the paper, the nearest-neighbour (NN) interconnection of switches within a multistage interconnection network (MIN) is analysed. Three main results are obtained: (1) The switch preserving transformation of a 2-D MIN into the 1-D MIN (and vice versa) (2) The rearrangeability of the MIN and (3) The number of stages (NS) for the rearrangeable nonblocking interconnection. The analysis is extended to any dimension of the interconnected data set. The topological equivalence between 1-D MINs with NN interconnections (NN-MINs) and 1-D cellular arrays is shown.

Long term phase noises are characterized for network synchronization using two time domain measurement techniques: the Maximum Time Interval Error (MTIE) and Time Variance (TVAR). First, the characteristics of previously measured fiber delay variations are evaluated. The diurnal and annual delay variations and the long term noise feature of random walk phase modulation are well represented by the TVAR technique. The delay variation due to the AU pointer operation is then measured using commercial SDH demultiplexing equipment and compared with the simulation result; the simulation result agrees well with the experimental result. The delay variation in the SDH equipment is simulated using the thermal fiber delay variation measured in the actual network as the input phase of the equipment. It is shown that the SDH equipment sometimes generates delay steps of 617ns, which are larger than the normal pointer operations of 154ns. The long term delay variation, periods over 107s, due to the threshold spacing between the positive and negative stuffing is described. We also show that TVAR is suitable for evaluating the phase noise feature and MTIE can clearly show the peak value of phase noise. The long term phase noises evaluated in this paper are the dominant sources that degrade network synchronous performance. The results of this paper will be useful in designing the equipment synchronous specification.

For a CBR (Constant Bit Rate) connection in an ATM (Asynchronous Transfer Mode) network, we determine the CDV (Cell Delay Variation) tolerance for the mapping of ATM cells from the ATM Layer onto the Physical Layer. Our result will be useful to properly allocate resources to connections and to accurately enforce the contract governing the user's cell traffic by UPC (Usage Parameter Control).

This paper compares three typical system-sharing configurations for FTTH networks that provide narrowband and video distribution services and proposes a remote node locating strategy for each configuration. Two new evaluation factors, required land space and service provisioning effort, are included in the calculation, in addition to facility cost and maintenance effort. By considering these factors together, the total network cost is calculated and the sensitivity to the number of remote nodes is evaluated. Finally, the most economical system-sharing configuration is identified on the basis of the evaluations for two typical service areas in Japan, for both present and future cost environments.

The FDDI-II is a high speed and flexible backbone LAN. It can divide the capacity into one packet-switched channel with flexible bandwidth and up to 16 isochronous channels which may be allocated for a variety of real-time services such as video and voice. How to allocate and maintain isochronous bandwidth is an important issue for supporting good services to users. The FDDI-II standard proposed a centralized scheme to achieve this goal. In this paper, we propose a new scheme in a distributed fashion for the management of isochronous bandwidth. Based on our scheme, the network can support various services in a more efficient way.

The validity of numerical design scheme of CP-PASS (Circularly Polarized Printed Array antenna composed of Strips and Slots) is considered. The strip element of CP-PASS is composed of a strip dipole and a window which increases the frequency bandwidth of the strip element. With the window, however, analysis of the antenna becomes difficult if a simple analytical model is used. The previous design procedure requierd an experimental procedure. By using modern computers, the FDTD (finite-difference time-domain) method becomes powerful tool for the analysis of 3D-structured antennas. In this paper, numerical results of the FDTD analysis for CP-PASS is compared with results from experiments. The characteristics of the unit-radiator of CP-PASS are demonstrated numerically. This paper shows that CP-PASS can be designed numerically and a new path has opened in the study of CP-PASS.

This paper presents the results of a study made to determine the line length coverage of the high-bit-rate digital subscriber line (HDSL) present in NTT's local networks. The HDSL carries one bi-directional 784 kbit/s channel per pair and supports the digital interface at 1544kbit/s by using two cable pairs. The primary purpose of this study is to estimate the range limits for candidate transmission schemes considering line installation conditions, and to determine the most promising transmission scheme and its feasibility given the environment of NTT's local networks. Pulse amplitude modulation (PAM) and quadrature amplitude modulation (QAM) transmission schemes are compared for HDSL implementation. It is shown that 2B1Q-PAM and 16-QAM generally achieve better performance than the more complicated PAM and QAM given the presence intra-system crosstalk interference (interference between identical transmission systems). The range limits determined by inter-system crosstalk interference (interference between different transmission systems) with basic rate access (BRA) implementing a burst-mode transmission method are also estimated. This paper concludes that 2B1Q-PAM achieves the best overall performance in NTT's local networks. A feasibility study of 192-6144 kbit/s transmission is also described.

A new approach is described for the datapath scheduling of behavioral descriptions containing nested conditional branches of arbitrary structures. This paper first investigates such a complex scheduling mechanism, and formulates an optimal scheduling problem as a 0-1 integer programming problem such that given a prescribed number of control steps, the total cost of functional units can be minimized. In this formulation, each constraint is expressed in the form of a Boolean function, which is set equal to 1 or 0 according as the constraint is satisfied or not, respectively, and a satisfiability problem is defined by the product of the Boolean functions. A procedure is then described, which intends to seek an optimal solution by means of a branch-and-bound method on a binary decision diagram representing the satisfiability problem. Experimental results are also shown, which demonstrate that our approach is of more practical use than the existing methods.

Video compression technologies such as MPEG have enabled the efficient use of video data in the computer environment. However, the compressed video information still has a huge amount of data compared with the other media such as text, audio, and graphics. Therefore, it is very important to handle the video information in a networked database for the efficient use of resources like storage media. Furthermore, in the networked database, its retrieval methods including search and delivery become the key issues especially for the video information which requires a large network bandwidth. In this paper, a video browsing method using an automatic fast scene cut detection for networked video database access is described. The scene cut is defined as the scene change frame and is detected by temporal change in interframe luminance difference and chrominance correlation which are obtained from spatio-temporally scaled image directly extracted from the MPEG compressed video without any complex processing of video decoding. The detected scene change frames are further investigated to exploit the relationship between the scene cuts and are classified in order to make a hierarchical indexing. These results of detection are stored as an scene index file using the MPEG format. The simulation results are also presented for several test video sequences to show that these methods have enabled the efficient video database construction and accessing.

This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.

A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.

This paper focuses on Mixed Reality (MR) visual displays, a particular subset of Virtual Reality (VR) related technologies that involve the merging of real and virtual worlds somewhere along the virtuality continuum" which connects completely real environments to completely virtual ones. Probably the best known of these is Augmented Reality (AR), which refers to all cases in which the display of an otherwise real environment is augmented by means of virtual (computer graphic) objects. The converse case on the virtuality continuum is therefore Augmented Virtuality (AV). Six classes of hybrid MR display environments are identified. However, an attempt to distinguish these classes on the basis of whether they are primarily video or computer graphics based, whether the real world is viewed directly or via some electronic display medium, whether the viewer is intended to feel part of the world or on the outside looking in, and whether or not the scale of the display is intended to map orthoscopically onto the real world leads to quite different groupings among the six identified classes, thereby demonstrating the need for an efficient taxonomy, or classification framework, according to which essential differences can be identified. The obvious' distinction between the terms real" and virtual" is shown to have a number of different aspects, depending on whether one is dealing with real or virtual objects, real or virtual images, and direct or non-direct viewing of these. An (approximately) three dimensional taxonomy is proposed, comprising the following dimensions: Extent of World Knowledge (how much do we know about the world being displayed?"), Reproduction Fidelity (how realistically' are we able to display it?"), and Extent of Presence Metaphor (what is the extent of the illusion that the observer is present within that world?").

Mixed-signal LSIs promise to permit increased levels of integration, not only in voiceband but also in multi-GHz-band applications such as wireless communications and optical data links. This paper reviews the evolution of mixed-signal communications LSIs and discusses some of their design problems, including device noise and crosstalk noise. In the low-power and low-voltage designs emerging as new disciplines, the target supply voltage for voiceband LSIs is around 1 V, and even GHz-band circuits are approaching 2 V. MOS devices are expected to play an important role even in the frequency range over 100 MHz, in the area of wireless or optical communications circuits.

This paper presents an analysis of the control characteristics of the series resonant converter with a parallel resonant circuit, especially under parallel resonant frequency. Operations of the circuit are classified into several modes. The control characteristics are calculated using the equations derived from equivalent circuits, and are verified by the experiments. From the analysis, the mechanism of a jumping phenomenon in the closed-loop control characteristics is clarified.

A single-chip architecture for three-dimensional (3-D) computer graphics (CG) is discussed assuming portable equipment with a 3-D CG interface. Based on a discussion of chip requirements, an architecture utilizing DRAM technology is proposed. A 31-Mbit, on-chip DRAM cell array allows a full-color, 480640-pixel frame with two 3-D frame buffers for double buffering and one 2-D frame buffer for superimposed or background images. The on-chip pixel generator produces R, G, B, and Z data in a triangular polygon with a zigzag-scan interpolation algorithm. The on-chip frame synthesizer combines data from one of the 3-D buffers with that from the 2-D buffer to produce superimposed or background 2-D images within a 3-D CG image. Parallel alpha-blending and Z-comparison circuits attached to the DRAM cell array provide a high data I/O rate. Estimation of the chip performance assuming the 0.35-µm CMOS design rule shows the chip size, the drawing speed, on-chip data I/O rate, and power dissipation would be 1413.5-mm, 0.25 million polygons/s, 1 gigabyte/s, and 590 mW at a voltage of 3.3 V, respectively. Based on circuit simulations, the chip can run on a 1.5-V dry cell with a drawing speed of 0.125 million polygons/s and a power dissipation of 61 mW. A scaled-down version of the chip which has an 1-kbit DRAM cell array with an attached alpha-blending circuit is being fabricated for evaluation.