This paper proposes a partial transmit sequences (PTS)-based PAPR reduction method and a phase factor estimation method without side information for OFDM systems with QPSK and 16QAM modulation. In the transmitter, an iterative algorithm that minimizes the p-norm of a transmitted signal determines phase factors to reduce PAPR. Unlike conventional methods, the phase factors are allowed to take continuous values in a limited range. In the receiver, the phase factor is blindly estimated by evaluating the phase differences between the equalizer's output and its closest constellation points. Simulation results show that the proposed PAPR reduction method is more computationally efficient than the conventional PTS. Moreover, the combined use of the two proposed methods achieves a satisfactory tradeoff between PAPR and BER by limiting the phase factors properly.

Network-listening-based synchronization is recently attracting attention as an effective timing synchronization method for indoor small-cell base stations as they cannot utilize GPS-based synchronization. It uses only the macro-cell downlink signal to establish synchronization with the overlaying macro cell. However, the loop-back signal from the small-cell base station itself interferes with the reception of the macro-cell downlink signal in the deployment of co-channel heterogeneous networks. In this paper, we investigate a synchronization method that avoids loop-back interference by muting small-cell data transmission and shifting small-cell transmission timing. Our proposal enables to reduce the processing burden of the network listening and mitigate the throughput degradation of the small cell caused by the data-transmission mutation. In addition to this, the network-listening system enables the network listening in dense small cell deployments where a large number of neighboring small cells exist. We clarify the performance of our proposal by computer simulations and laboratory experiments on actual equipment.

Software-defined networking (SDN) has emerged as a promising approach to enable network innovation, which can provide network virtualization through a hypervisor plane to share the same cloud datacenter network among multiple virtual networks. While, this attractive approach may bring some new problem that leads to more susceptible to the failure of network component because of the separated control and forwarding planes. The centralized control and virtual network sharing the same physical network are becoming fragile and prone to failure if the topology of virtual network and the control path is not properly designed. Thus, how to map virtual network into physical datacenter network in virtualized SDN while guaranteeing the survivability against the failure of physical component is extremely important and should fully consider more influence factors on the survivability of virtual network. In this paper, combining VN with SDN, a topology-aware survivable virtual network embedding approach is proposed to improve the survivability of virtual network by an enhanced virtual controller embedding strategy to optimize the placement selection of virtual network without using any backup resources. The strategy explicitly takes account of the network delay and the number of disjoint path between virtual controller and virtual switch to minimize the expected percentage of control path loss with survivable factor. Extensive experimental evaluations have been conducted and the results verify that the proposed technology has improved the survivability and network delay while keeping the other within reasonable bounds.

In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

Phase locking with frequency tuning is demonstrated for a resonant-tunneling-diode terahertz oscillator integrated with a biased varactor diode. The tuning range of oscillation frequency is 606-613GHz. The phase noise in the output of the oscillator is transformed to amplitude noise, and fed back to the varactor diode together with bias voltage. The spectral linewidth at least <2Hz was obtained at the oscillation frequencies tuned by the bias voltage of the varactor diode.

In this paper, we study parallel join processing to improve the performance of the merge phase of sort-merge join by integrating all parallelism provided by mainstream CPUs. Modern CPUs support SIMD instruction sets with wider SIMD registers which allows to process multiple data items per each instruction. Thus, we devise an efficient parallel join algorithm, called Parallel Merge Join with SIMD instructions (PMJS). In our proposed algorithm, we utilize data parallelism by exploiting SIMD instructions. And we also accelerate the performance by avoiding the usage of conditional branch instructions. Furthermore, to take advantage of the multiple cores, our proposed algorithm is threaded in multi-thread environments. In our multi-thread algorithm, to distribute workload evenly to each thread, we devise an efficient workload balancing algorithm based on the kernel density estimator which allows to estimate the workload of each thread accurately.

This paper proposes an iterative scheme between human action classification and pose estimation in still images. Initial action classification is achieved only by global image features that consist of the responses of various object filters. The classification likelihood of each action weights human poses estimated by the pose models of multiple sub-action classes. Such fine-grained action-specific pose models allow us to robustly identify the pose of a target person under the assumption that similar poses are observed in each action. From the estimated pose, pose features are extracted and used with global image features for action re-classification. This iterative scheme can mutually improve action classification and pose estimation. Experimental results with a public dataset demonstrate the effectiveness of the proposed method both for action classification and pose estimation.

We have proposed a fish-farm monitoring system. In our system, the transmission range of acoustic waves from sensors attached to the undersides of the fish is not omnidirectional because of obstruction from the bodies of the fish. In addition, energy-efficient control is highly important in our system to avoid the need to replace the batteries. In this letter, we propose a data-gathering method for fish-farm monitoring without the use of control packets so that energy-efficient control is possible. Instead, our method uses the transmission-range volume as calculated from the location of the sensor node to determine the timing of packet transmission. Through simulation evaluations, we show that the data-gathering performance of our proposed method is better than that of comparative methods.

A grammar compression is a restricted context-free grammar (CFG) that derives a single string deterministically. The goal of a grammar compression algorithm is to develop a smaller CFG by finding and removing duplicate patterns, which is simply a frequent pattern discovery process. Any frequent pattern can be obtained in linear time; however, a huge working space is required for longer patterns, and the entire string must be preloaded into memory. We propose an online algorithm to address this problem approximately within compressed space. For an input sequence of symbols, a1,a2,..., let Gi be a grammar compression for the string a1a2…ai. In this study, an online algorithm is considered one that can compute Gi+1 from (Gi,ai+1) without explicitly decompressing Gi. Here, let G be a grammar compression for string S. We say that variable X approximates a substring P of S within approximation ratio δ iff for any interval [i,j] with P=S[i,j], the parse tree of G has a node labeled with X that derives S[l,r] for a subinterval [l,r] of [i,j] satisfying |[l,r]|≥δ|[i,j]|. Then, G solves the frequent pattern discovery problem approximately within δ iff for any frequent pattern P of S, there exists a variable that approximates P within δ. Here, δ is called the approximation ratio of G for S. Previously, the best approximation ratio obtained by a polynomial time algorithm was Ω(1/lg2|P|). The main contribution of this work is to present a new lower bound Ω(1/<*|S|lg|P|) that is smaller than the previous bound when lg*|S|

We propose an algorithm for the gathering problem of mobile agents in arbitrary networks (graphs) with Byzantine agents. Our algorithm can make all correct agents meet at a single node in O(fm) time (f is the upper bound of the number of Byzantine agents and m is the number of edges) under the assumption that agents have unique ID and behave synchronously, each node is equipped with an authenticated whiteboard, and f is known to agents. Here, the whiteboard is a node memory where agents can leave information. Since the existing algorithm achieves gathering without a whiteboard in Õ(n9λ) time, where n is the number of nodes and λ is the length of the longest ID, our algorithm shows an authenticated whiteboard can significantly reduce the time for the gathering problem in Byzantine environments.

The next generation wireless LAN standard IEEE 802.11ax aims to provide improved throughput performance in dense environments. We have proposed an efficient channel sounding mechanism for DL-MU-MIMO that has been adopted as a new sounding protocol in the 802.11ax standard. In this paper, we evaluate the overhead reduction in the 802.11ax sounding protocol compared with the 802.11ac sounding protocol. Sounding is frequently performed to obtain accurate channel information from the associated stations in order to improve overall system throughput. However, there is a trade-off between accurate channel information and the overhead incurred due to frequent sounding. Therefore, the sounding interval is an important factor that determines system throughput in DL-MU-MIMO transmission. We also evaluate the effect of sounding interval on the system throughput performance using both sounding protocols and provide a comparative analysis of the performance improvement.

IEEE 802.11ah is a new wireless standard for large-scale wireless connectivity in IoT and M2M applications. One of the major requirements placed on IEEE 802.11ah is the energy-efficient communication of several thousand stations with a single access point. This is especially difficult to achieve during network initialization, because the several thousand stations must rely on the rudimentary approach of random channel access, and the inevitable increase in channel access contention yields a long association delay. IEEE 802.11ah has introduced an authentication control mechanism that classifies stations into groups, and only a small number of stations in a group are allowed to access the medium at a time. Although the grouping strategy provides fair channel access to a large number of stations, the presence of several thousand stations and limitation that only a group can use the channel at a time, causes the association time to remain excessive. In this paper, we propose a novel block association method that enables simultaneous association of all groups. Our experiments verify that our block association method decreases the total association time by many folds.

The conventional generalized spatial modulation (GSM) simultaneously activates multiple transmit antennas in order to improve the spectral efficiency of the original SM. In this letter, to lessen the hardware burden of the multiple RF chains, we provide a new scheme that is designed by combining the GSM scheme using only two active antennas with quaternary quasi-orthogonal sequences of a length of two. Compared with the other SM schemes, the proposed scheme has significant benefits in average error performances and/or their hardware complexities of the RF systems.

In this paper, we propose a Mobile Edge Internet of Things (MEIoT) architecture by leveraging the fiber-wireless access technology, the cloudlet concept, and the software defined networking framework. The MEIoT architecture brings computing and storage resources close to Internet of Things (IoT) devices in order to speed up IoT data sharing and analytics. Specifically, the IoT devices (belonging to the same user) are associated to a specific proxy Virtual Machine (VM) in the nearby cloudlet. The proxy VM stores and analyzes the IoT data (generated by its IoT devices) in real-time. Moreover, we introduce the semantic and social IoT technology in the context of MEIoT to solve the interoperability and inefficient access control problem in the IoT system. In addition, we propose two dynamic proxy VM migration methods to minimize the end-to-end delay between proxy VMs and their IoT devices and to minimize the total on-grid energy consumption of the cloudlets, respectively. Performance of the proposed methods is validated via extensive simulations.

Peer-to-peer overlay networks can easily achieve a large-scale content sharing system on the Internet. Although unstructured peer-to-peer networks are suitable for finding entire partial-match content, flooding-based search is an inefficient way to obtain target content. When the shared content is semantically specified by a great number of attributes, it is difficult to derive the semantic similarity of peers beforehand. This means that content search methods relying on interest-based locality are more advantageous than those based on the semantic similarity of peers. Existing search methods that exploit interest-based locality organize multiple peer groups, in each of which peers with common interests are densely connected using short-cut links. However, content searches among multiple peer groups are still inefficient when the number of incident links at each peer is limited due to the capacity of the peer. This paper proposes a novel content search method that exploits interest-based locality. The proposed method can organize an efficient peer-to-peer network similar to the semantic small-world random graph, which can be organized by the existing methods based on the semantic similarity of peers. In the proposed method, topology transformation based on local link replacement maintains the numbers of incident links at all the peers. Simulation results confirm that the proposed method can achieve a significantly higher ratio of obtainable partial-match content than existing methods that organize peer groups.

Major cloud service providers, including Amazon and Microsoft, have started employing field-programmable gate arrays (FPGAs) to build high-performance and low-power-consumption cloud capability. However, utilizing an FPGA-enabled cloud is still challenging because of two main reasons. First, the introduction of software and hardware co-design leads to high development complexity. Second, FPGA virtualization and accelerator scheduling techniques are not fully researched for cluster deployment. In this paper, we propose an open-source FPGA-as-a-service (FaaS) platform, the hCODE, to simplify the design, management and deployment of FPGA accelerators at cluster scale. The proposed platform implements a Shell-and-IP design pattern and an open accelerator repository to reduce design and management costs of FPGA projects. Efficient FPGA virtualization and accelerator scheduling techniques are proposed to deploy accelerators on the FPGA-enabled cluster easily. With the proposed hCODE, hardware designers and accelerator users can be organized on one platform to efficiently build open-hardware ecosystem.

Deep neural network (DNN)-based speech synthesis can produce more natural synthesized speech than the conventional HMM-based speech synthesis. However, it is not revealed whether the synthesized speech quality can be improved by utilizing a multi-speaker speech corpus. To address this problem, this paper proposes DNN-based speech synthesis using speaker codes as a method to improve the performance of the conventional speaker dependent DNN-based method. In order to model speaker variation in the DNN, the augmented feature (speaker codes) is fed to the hidden layer(s) of the conventional DNN. This paper investigates the effectiveness of introducing speaker codes to DNN acoustic models for speech synthesis for two tasks: multi-speaker modeling and speaker adaptation. For the multi-speaker modeling task, the method we propose trains connection weights of the whole DNN using a multi-speaker speech corpus. When performing multi-speaker synthesis, the speaker code corresponding to the selected target speaker is fed to the DNN to generate the speaker's voice. When performing speaker adaptation, a set of connection weights of the multi-speaker model is re-estimated to generate a new target speaker's voice. We investigated the relationship between the prediction performance and architecture of the DNNs through objective measurements. Objective evaluation experiments revealed that the proposed model outperformed conventional methods (HMMs, speaker dependent DNNs and multi-speaker DNNs based on a shared hidden layer structure). Subjective evaluation experimental results showed that the proposed model again outperformed the conventional methods (HMMs, speaker dependent DNNs), especially when using a small number of target speaker utterances.

Studies have shown that program visualization(PV) is effective for student programming exercise or self-study support. However, very few instructors actively use PV tools for programming lectures. This article discussed the impediments the instructors meet during combining PV tools into lecture classrooms and proposed a C programming classroom instruction support tool based on program visualization — PROVIT-CI (PROgram VIsualization Tool for Classroom Instruction). PROVIT-CI has been consecutively and actively used by the instructors in author's university to enhance their lectures since 2015. The evaluation of application results in an introductory C programming course shows that PROVIT-CI is effective and helpful for instructors classroom use.

An optimal design method for a sub-ranging Analog-to-Digital Converter (ADC) based on stochastic comparator is demonstrated by performing theoretical analysis of random comparator offset voltages. If the Cumulative Distribution Function (CDF) of the comparator offset is defined appropriately, we can calculate the PDFs of the output code and the effective resolution of a stochastic comparator. It is possible to model the analog-to-digital conversion accuracy (defined as yield) of a stochastic comparator by assuming that the correlations among the number of comparator offsets within different analog steps corresponding to the Least Significant Bit (LSB) of the output transfer function are negligible. Comparison with Monte Carlo simulation verifies that the proposed model precisely estimates the yield of the ADC when it is designed for a reasonable target yield of >0.8. By applying this model to a stochastic comparator we reveal that an additional calibration significantly enhances the resolution, i.e., it increases the Number of Bits (NOB) by ∼ 2 bits for the same target yield. Extending the model to a stochastic-comparator-based sub-ranging ADC indicates that the ADC design parameters can be tuned to find the optimal resource distribution between the deterministic coarse stage and the stochastic fine stage.

Field-programmable gate array (FPGA) devices are applied for accelerating specific calculations and reducing power consumption in a wide range of areas. One of the challenges associated with FPGAs is reducing static power for enforcing their power effectiveness. We propose a method involving fine-grained reconfiguration of body biases of logic and net resources to reduce the static power of FPGA devices. In addition, we develop an FPGA device called Flex Power FPGA with SOTB technology and demonstrate its power reduction function with a 32-bit counter circuit. In this paper, we describe the construction of an experimental platform to precisely evaluate power consumption and the maximum operating frequency of the device under various operating voltages and body biases with various practical circuits. Using the abovementioned platform, we evaluate the Flex Power FPGA chip at operating voltages of 0.5-1.0 V and at body biases of 0.0-0.5 V. In the evaluation, we use a 32-bit adder, 16-bit multiplier, and an SBOX circuit for AES cryptography. We operate the chip virtually with uniformed body bias voltage to drive all of the logic resources with the same threshold voltage. We demonstrate the advantage of the Flex Power FPGA by comparing its performance with non-reconfigurable biasing.