The metallic waveguide is one of many effective media for millimeter- and submillimeter-waves because of the advantage of its low-loss nature. This paper describes the fabrication method of PTFE-filled waveguide components with the use of the SR (synchrotron radiation) direct etching process of PTFE, sputter deposition of metal, and electroplating. PTFE is known as a difficult material to process with high precision. However, it has been reported that PTFE microstructures can be fabricated by the direct exposure to SR. First, an iris-coupled waveguide BPF with 5-stage Chebyshev response is designed and fabricated for the Q-band. It is demonstrated that the present process is applicable for the fabrication of the practical components inclusive of narrow patterns. Then, a cruciform 3 dB coupler with air-filled posts is designed and fabricated for the Q-band. Directivity and matched state of the coupler can be realized by “holes” in the dielectric material. The measurement results are also shown.

This paper proposes an adaptive algorithm for adaptive arrays that minimizes the bit error rate (BER) of the array output signals in radio communication systems with the use of multilevel modulation signals. In particular, amplitude phase shift keying (APSK) is used as one type of multilevel modulations in this paper. Simultaneous non-linear equations that are satisfied by the optimum weight vector of the proposed algorithm are derived and used for theoretical analyze of the performance of the adaptive array based on the proposed algorithm. As a result of the theoretical analysis, it can be shown that the proposed adaptive array improves the carrier to interference ratio of the array output signal without taking advantage of the nulls. Furthermore, it is confirmed that the result of the theoretical analysis agrees with that of computer simulation. When the number of the received antenna is less than that of the received signals, the adaptive array based on the proposed algorithm is verified to achieve much better performance then that based on the least mean square (LMS) algorithm.

The electric field mill in our underground observation room detected a co-seismic electromagnetic signal in the vertical electrostatic field ca. 8 s after the origin time of the Niigataken Chuetsu-oki Earthquake in 2007, but ca. 30 s before the arrival time of the P-waves.

A total-field/scattered-field (TF/SF) boundary for the constrained interpolation profile (CIP) method is proposed for multi-dimensional electromagnetic problems. Incident fields are added to or subtracted from update equations in order to satisfy advection equations into which Maxwell's equations are reduced by means of the directional splitting. Modified incident fields are introduced to take into account electromagnetic fields after advection. The developed TF/SF boundary is examined numerically, and the results show that it operates with good performance. Finally, we apply the proposed TF/SF boundary to a scattering problem, and it can be solved successfully.

In this letter, we propose a novel speech enhancement algorithm based on data-driven residual gain estimation. The entire system consists of two stages. At the first stage, a conventional speech enhancement algorithm enhances the input signal while estimating several signal-to-noise ratio (SNR)-related parameters. The residual gain, which is estimated by a data-driven method, is applied to further enhance the signal at the second stage. A number of experimental results show that the proposed speech enhancement algorithm outperforms the conventional speech enhancement technique based on soft decision and the data-driven approach using SNR grid look-up table.

In off-line analysis, the demand for high precision signal processing has introduced a new method called Empirical Mode Decomposition (EMD), which is used for analyzing a complex set of data. Unfortunately, EMD is highly compute-intensive. In this paper, we show parallel implementation of Empirical Mode Decomposition on a GPU. We propose the use of “partial+total” switching method to increase performance while keeping the precision. We also focused on reducing the computation complexity in the above method from O(N) on a single CPU to O(N/P log (N)) on a GPU. Evaluation results show our single GPU implementation using Tesla C2050 (Fermi architecture) achieves a 29.9x speedup partially, and a 11.8x speedup totally when compared to a single Intel dual core CPU.

In the Long-Term Evolution (LTE)-Advanced downlink, a user-specific demodulation reference signal (DM-RS) is used to support channel estimation and data demodulation for user-transparent multi-antenna and/or multi-point (MA/P) transmission techniques. A hybrid code division multiplexing (CDM) and frequency division multiplexing (FDM) scheme is adopted as a DM-RS multiplexing scheme for up to eight data streams per user. A time-domain orthogonal cover code (OCC) is used for CDM since time domain orthogonality among OCCs offers good robustness against channel variation. However, in a medium-to-high mobility environment, orthogonality distortion occurs among OCCs, which results in performance degradation. In this paper, we propose a two-dimensional (2D)-OCC mapping that achieves two-dimensional orthogonality in the time and frequency domains to improve the performance of CDM-based DM-RSs while reducing the peak transmission power of the OFDM symbol which includes the DM-RSs. Simulation results show that the proposed 2D-OCC mapping is effective in improving the block error rate performance especially in medium-to-high mobility environments. Furthermore, it is shown that the 2D-OCC mapping effectively reduces the peak power compared to the time-domain OCC mapping.

Network testbeds have been used for network measurement and experiments. In such testbeds, resources, such as CPU, memory, and I/O interfaces, are shared and virtualized to maximize node utility for many users. A few studies have investigated the impact of virtualization on precise network measurement and understood Internet traffic characteristics on virtualized testbeds. Although scheduling latency and heavy loads are reportedly affected in precise network measurement, no clear conditions or criteria have been established. Moreover, empirical-statistical criteria and methods that pick out anomalous cases for precise network experiments are required on userland because virtualization technology used in the provided testbeds is hardly replaceable. In this paper, we show that ‘oversize packet spacing’, which can be caused by CPU scheduling latency, is a major cause of throughput instability on a virtualized network testbed even when no significant changes occur in well-known network metrics. These are unusual anomalies on virtualized network environment. Empirical-statistical analysis results accord with results at previous work. If network throughput is decreased by the anomalies, we should carefully review measurement results. Our empirical approach enables anomalous cases to be identified. We present CPU availability as an important criterion for estimating the anomalies.

We consider Downlink (DL) scheduling for a multi-user cooperative cellular system with fixed relays. The conventional scheduling trend is to avoid interference by allocating orthogonal radio resources to each user, although simultaneous allocation of users on the same resource has been proven to be superior in, e.g., the broadcast channel. Therefore, we design a scheduler where in each frame, two selected relayed users are supported simultaneously through the Superposition Coding (SC) based scheme proposed in this paper. In this scheme, the messages destined to the two users are superposed in the modulation domain into three SC layers, allowing them to benefit from their high quality relayed links, thereby increasing the sum-rate. We derive the optimal power allocation over these three layers that maximizes the sum-rate under an equal rates' constraint. By integrating this scheme into the proposed scheduler, the simulation results show that our proposed SC scheduler provides high throughput and rate outage probability performance, indicating a significant fairness improvement. This validates the approach of simultaneous allocation versus orthogonal allocation in the cooperative cellular system.

Secrecy on the physical layer is receiving increased research interest due to its theoretical and practical importance. In this letter, a subcarrier allocation scheme is proposed for physical-layer security in cooperative orthogonal frequency division multiple access (OFDMA) networks that use the Amplify-and-Forward (AF) strategy. We consider the subcarrier pairing and assignment to maximize overall system rates subject to a secrecy level requirement. Monte Carlo simulations are carried out to validate our analysis.

Integration of optical paths and packets in a switch is a key technique to support ultra-high-speed traffic in the future Internet. However, the question of how to efficiently allocate wavelengths for optical paths and optical packets has not been solved yet due to the lack of a systematic model to evaluate the performance of the integrated switch. In this paper, we model the operation of the integrated switch as a system of two queuing models: M/M/x/x for optical paths and M/M/1/LPS for optical packets. From the model, we find an optimal policy to dynamically allocate wavelength resources in an integrated switch. Simulation results demonstrate that our mechanism achieves better performance than other methods.

We propose a novel technique to grow the single-walled carbon nanotubes (SWNTs) with specific chirality at the desired position using free electron laser (FEL) irradiation during growth and surface treatment. As a result, only the semiconducting SWNTs grew at the area between triangle electrodes, where the ozone treatment was done to be hydrophilic when an alcohol chemical vapor deposition (ACCVD) process was carried out with the 800 nm FEL irradiation. Although the number of possible chiral index is 22 in the SWNTs grown without the FEL irradiation, the number is much reduced to be 8 by the FEL.

In this letter, we show that the code-trellis and the error-trellis for a convolutional code can be reduced simultaneously, if reduction is possible. Assume that the error-trellis can be reduced by shifting particular error-subsequences. In this case, if the identical shifts occur in the corresponding subsequences of each code-path, then the code-trellis can also be reduced. First, we obtain pairs of transformations which generate the identical shifts both in the subsequences of the code-path and in those of the error-path. Next, by applying these transformations to the generator matrix and the parity-check matrix, we show that reduction of these matrices is accomplished simultaneously, if it is possible. Moreover, it is shown that the two associated trellises are also reduced simultaneously.

Based on the substrate integrated waveguide (SIW) technology, a new type of varactor-tuned radial power divider has been developed with a single bias supply. The varactors are used as tuning elements and allow for a frequency agile behavior. In addition, bandwidth characteristics have been analysed with group-delay. It has been measured with a single bias supply ranging from 6 V to 12 V that the center frequency of the power divider can be adjusted from 6.6 GHz to 7.2 GHz (600 MHz, 11.5%) while maintaining a low insertion loss (< 1 dB) in the passband.

We propose a capacitive averaging technique applied to a double-tail latched comparator without a preamplifier for an offset reduction technique. Capacitive averaging can be introduced by considering the first stage of the double-tail latched comparator as a capacitive loaded amplifier. This makes it possible to reduce the offset voltage while preventing an increase in power dissipation. A positive feedback technique is also used for the first stage, which maximizes the effectiveness of the capacitive averaging. The capacitive averaging mechanism and the relationship between the offset reduction and the linearity of the amplifier is discussed in detail. Simulation results for a 90-nm CMOS process show that the proposed technique can reduce the offset voltage by 1/3.5 (3 mV) at a power dissipation of only 45 µW.

Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.

To characterize and predict the dynamics of the nonlinear polarization rotation in SOAs, an experimental method based on the frequency response technique and a model based on the density matrix and effective index formalisms are presented. Both determine the angular displacement, at the Poincare Sphere, that produces the evolution of the polarization of the output signal.

To estimate the field emission current associated with an array of carbon nanowalls (CNWs), the model of the floating rods between anode and cathode plates was proposed. An approximate formula for the enhancement factor was derived, showing that the interwall distance of the CNW array critically affects the field emission. The field enhancement factor was almost one order of magnitude less than that of vertically aligned CNTs. Considering the field emission current density, the field emission can be optimized when the interwall distance is comparable with the wall height. For same separation distance, the macroscopic field strength of the CNW array is almost one order of magnitude higher than that of vertical CNT array to obtain the emission current of 1 mA from the cathode surface of 1 cm2.

Iterative synthesis methods for making aware of wire congestion are proposed for a multi-context dynamically reconfigurable processor (DRP) with a large number of processing elements (PEs) and programmable-wire connections. Although complex data-paths can be synthesized using the programmable-wire, its delay is long especially when wire connections are congested. We propose two iterative synthesis techniques between a high-level synthesizer (HLS) and the place & route tool to shorten the prolonged wire delay. First, we feed back wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten by 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on the congestion. The synthesis time was shorten to 1/3 causing delay improvement rate degradation at two points on average.

We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90 different angles. The designs in a 180-nm CMOS process and a 65-nm CMOS process were fabricated to confirm its process scalability; in the respective designs, we observed 36.6% and 38.3% improvements in a power-delay products, compared with the conventional MPOSCs using inverters and nMOS latches. In a 65-nm process, the measured DNL and 3σ period jitter are, respectively, less than 1.22 and 5.82 ps. The power is 284 µW at 1.85 GHz.