The IEEE 802.15.4 protocol is considered a promising technology for low-cost low-power wireless personal area networks. Researchers have discussed the feasibility of voice communications over IEEE 802.15.4 networks. To this end, the personal area network (PAN) coordinator allocates guaranteed time slots (GTSs) for voice communications in the beacon-enabled mode of IEEE 802.15.4. Although IEEE 802.15.4 is capable of supporting voice communications by GTS allocation, it is impossible to accommodate voice transmission beyond two hops due to the excessive transmission delay. In this paper, we propose a GTS allocation scheme for bidirectional voice traffic in IEEE 802.15.4 multihop networks. The goal of our proposed scheme is to achieve low end-to-end delay and packet drop ratio without a complex allocation algorithm. Thus, the proposed scheme allocates GTSs to devices for successful completion of voice transmission in a superframe duration. The proposed scheme also considers transceiver switching delay. This is relatively large compared to a time slot due to the low-cost and low-gain antenna designs. We analyze and validate the proposed scheme in terms of average end-to-end delay and packet drop ratio. Our scheme has lower end-to-end delay and packet drop ratio than the basic IEEE 802.15.4 GTS allocation scheme.

Because of numerous circuit resources of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to reduce the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. The results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this analysis, we develop COGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area of 4-COGRE is smaller than that of 4-LUT and 5-LUT by approximately 35.79% and 54.70%, respectively. The logic area of 8-COGRE is 75.19% less than that of 8-LUT. Further, the total number of configuration memory bits of 4-COGRE is 8.26% less than the number of configuration memory bits of 4-LUT. The total number of configuration memory bits of 8-COGRE is 68.27% less than the number of configuration memory bits of 8-LUT.

The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.

This paper suggests an outphasing scheme to reduce adjacent channel spectral regrowth triggered by the gain and phase mismatch between two signal paths in linear amplification with nonlinear component (LINC) systems. The error vector magnitude and power spectral density of the output signal considering path mismatch are described analytically using path mismatch factor. An outphasing scheme is proposed to reduce the spectral regrowth. The proposed outphasing scheme reshapes the phases of the separated signals in LINC systems to reduce the changes of the phases. Its performance is verified by performing simulations with multi-tone signals. The result shows that the scheme can reduce the spectral regrowth of the multi-tone signals significantly compared to the conventional outphasing scheme for LINC systems with path imbalance.

In this paper, a new Hammerstein predistorter modeling for power amplifier (PA) linearization is proposed. The key feature of the model is that the cubic splines, instead of conventional high-order polynomials, are utilized as the static nonlinearities due to the fact that the splines are able to represent hard nonlinearities accurately and circumvent the numerical instability problem simultaneously. Furthermore, according to the amplifier's AM/AM and AM/PM characteristics, real-valued cubic spline functions are utilized to compensate the nonlinear distortion of the amplifier and the following finite impulse response (FIR) filters are utilized to eliminate the memory effects of the amplifier. In addition, the identification algorithm of the Hammerstein predistorter is discussed. The predistorter is implemented on the indirect learning architecture, and the separable nonlinear least squares (SNLS) Levenberg-Marquardt algorithm is adopted for the sake that the separation method reduces the dimension of the nonlinear search space and thus greatly simplifies the identification procedure. However, the convergence performance of the iterative SNLS algorithm is sensitive to the initial estimation. Therefore an effective normalization strategy is presented to solve this problem. Simulation experiments were carried out on a single-carrier WCDMA signal. Results show that compared to the conventional polynomial predistorters, the proposed Hammerstein predistorter has a higher linearization performance when the PA is near saturation and has a comparable linearization performance when the PA is mildly nonlinear. Furthermore, the proposed predistorter is numerically more stable in all input back-off cases. The results also demonstrate the validity of the convergence scheme.

This letter focuses on the design of selective receivers for homogeneous scenarios where a very small number of secondary data are available. To this end, at the design stage it is assumed that the cell under test (CUT) contains a fictitious signal orthogonal to the nominal steering vector under the null hypothesis; the clutter covariance matrix is modeled as a random matrix with an inverse complex Wishart distribution. Under the above assumptions, we devise two Bayesian detectors based on the GLRT criterion, both one-step and two-step. It is shown that the proposed detectors have the same detection structure as their non-Bayesian counterparts, substituting the colored diagonal sample covariance matrix (SCM) for the classic one. Finally, a performance assessment, conducted by Monte Carlo simulations, has shown that our detectors ensure better rejection capabilities of mismatched signals than the existing Bayesian detectors, at the price of a certain loss in terms of detection of matched signals.

In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.

This paper proposes a dual-conduction class-C VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed. These NMOS pairs realize an impulse-like current waveform to improve the phase noise in the low supply conditions. The proposed VCO was implemented in a standard 0.18 µm CMOS technology, which oscillates at a carrier frequency of 4.5 GHz with a 0.2-V supply voltage. The measured phase noise is -104 dBc/Hz@1 MHz-offset with a power consumption of 114 µW, and the FoM is -187 dBc/Hz.

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

This paper considers the discrete model of the cart-pendulum system modeled by discrete mechanics, which is known as a good discretizing method for mechanical systems and has not been really applied to control theory. We first sum up basic concepts on discrete mechanics and discuss the explicitness of the linear approximation of the discrete Euler-Lagrange Equations. Next, the discrete cart-pendulum system is derived and analyzed from the viewpoint of solvability of implicit nonlinear control systems. We then show a control algorithm to stabilize the discrete cart-pendulum based on the discrete-time optimal regulator theory. Finally, some simulations are shown to demonstrate the effectiveness of the proposed algorithm.

Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

This paper presents an ultra-wideband (UWB) bandpass filter (BPF) with sharp attenuation slope characteristics. The circuit structure consists of an inter-digital finger resonator, parallel-coupled lines and phase matching line. The design of the bandwidth was described by using the even and odd mode characteristic impedances in the resonator structure. The parallel-coupled lines were also designed in the same manner. The parameters of the resonator and two parallel-coupled lines in combination as the BPF were then optimized by the simulation with HFSS. The designed BPF was experimentally fabricated and its measured performances showed the bandwidth from 3.6 to 10 GHz with the 20 dB outband rejection. For the U.S. UWB band design, the matching line was inserted between the two parallel-coupled lines. The matching at both band edges was then qualitatively analyzed on the smithchart. The HFSS simulation results of the structure realized the bandwidth from 3.1 to 10.6 GHz with sharp attenuation slope characteristics for SWR < 2.0. The measurement results agree well with the simulation results.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

We demonstrate the wavelength trimming of MEMS VCSELs by etching a cantilever-shaped top mirror using FIB etching. The proposed technique can be used for the post-process precise wavelength allocation of athermal MEMS VCSELs. The modeling and experimental results on 850 nm MEMS VCSELs are presented. The results show a possibility of realizing both red-shift and blue-shift wavelength changes by choosing the etching area of the cantilever.

In this paper, a sepic-type single-stage electronic ballast (STSSEB) is proposed, which is derived from the combination of a sepic converter and a half-bridge inverter. The ballast can not only step down input voltage directly but achieve high power factor, reduce voltage stress, improve efficiency and lower cost. Since component stress is reduced significantly, the presented ballast can be applied to high voltage mains. Derivation of the STSSEB is first presented. Then, analysis, design and practical consideration for the STSSEB are discussed. A 347 Vac 60 W prototype has been simulated and implemented. Simulations and experimental results have verified the feasibility of the proposed STSSEB.

We introduce the distributed estimation of a random vector signal in wireless sensor networks that follow coherent multiple access channel model. We adopt the linear minimum mean squared error fusion rule. The problem of interest is to design linear coding matrices for those sensors in the network so as to minimize mean squared error of the estimated vector signal under a total power constraint. We show that the problem can be formulated as a convex optimization problem and we obtain closed form expressions of the coding matrices. Numerical results are used to illustrate the performance of the proposed method.

This paper proposes a utility function-based scheduling algorithm for integrated real-time and non-real-time services in long-term evolution systems. The proposed utility function satisfies the target dropping ratio of real-time users; it uses the delay constraint and increases the throughput of non-real-time users by scheduling real-time users together with non-real-time users. Simulation results show that the proposed scheduling algorithm significantly improves the throughput of non-real-time users without sacrificing the quality of service of real-time users.

We consider secure wireless communications, where a source is communicating to a destination in the presence of K (K > 1) eavesdroppers. The source and destination both are equipped with multiple antennas, while each eavesdropper has a single antenna. The source aims to maximize the communication rate to the destination, while concealing the message from all the eavesdroppers. Combined with selective diversity, we propose a heuristic secrecy transmission scheme where the multiple-input-multiple-output (MIMO) secrecy channel is simplified into a multiple-input-single-output (MISO) one with the highest orthogonality to the eavesdropper channels. Then convex optimization is applied to obtain the optimal transmit covariance matrix for this selected MISO secrecy channel. Numerical results are provided to illustrate the efficacy of the proposed scheme.

This letter proposes a practical algorithm for video transmission of the scalable extension of H.264/AVC (SVC) over limited bit-rate and varying channel signal-to-noise ratio (SNR). The proposal consists of SVC source-layer dropping and layered FEC using LDPC codes to maximize the video quality. The experimental results show that the proposed method realizes better video quality than the compared unequal error protection (UEP) without source-layer dropping. This implies that the dropping of a certain number of source-layers and using the resultant bit-budget for channel coding is more effective than the other UEP case which uses all possible source-layers.

An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.