In the framework of supervisory control of timed discrete event systems (TDESs), a supervisor decides the set of events to be enabled to occur and the set of events to be forced to occur in order for a given specification to be satisfied. In this paper, we consider decentralized supervisory control of TDESs where enforcement decisions of local supervisors are fused by the AND rule or the OR rule. We derive existence conditions of a decentralized supervisor under these decision fusion rules.

A simple analytical model to predict the DC MOSFET behavior under electromagnetic interference (EMI) is presented. The model is able to describe the MOSFET performance in the linear and saturation regions under EMI disturbance applied to the gate. The model consists of a unique simple equivalent circuit based on a voltage dependent current source and a reduced number of parameters which can accurately predict the drift on the drain current due to the EMI source. The analytical approach has been validated by means of electric simulation and measurements and can be easily introduced in circuit simulators. The proposed modeling technique combined with the nth-power law model of the MOSFET without EMI, significantly improves its accuracy in comparison with the n-th power law directly applied to a MOSFET under EMI impact.

The statistical static timing analysis has been studied intensively in the last decade so as to deal with the process variability, and various techniques to represent distributions of timing information, such as a gate delay, a signal arrival time, and a slack, have been proposed. Among them, the Gaussian mixture model is distinguished from the others in that it can handle various correlations, non-Gaussian distributions, and slew distributions easily. However, the previous algorithm of computing the statistical maximum for Gaussian mixture models, which is one of key operations in the statistical static timing analysis, has a defect such that it produces a distribution similar to Gaussian in a certain case, although the correct distribution is far from Gaussian. In this paper, we propose a new algorithm for statistical maximum (minimum) operation for Gaussian mixture models. It takes the cumulative distribution function curve into consideration so as to compute accurate criticalities (probabilities of timing violation), which is important for detecting delay faults and circuit optimization with the use of statistical approaches. We also show some experimental results to evaluate the performance of the proposed method.

In automated transport applications, the design of a task allocation policy becomes a complex problem when there are several agents in the system and conflicts between them may arise, affecting the system's performance. In this situation, to achieve a globally optimal result would require the complete knowledge of the system's model, which is infeasible for real systems with huge state spaces and unknown state-transition probabilities. Reinforcement Learning (RL) methods have done well approximating optimal results in the processing of tasks, without requiring previous knowledge of the system's model. However, to our knowledge, there are not many RL methods focused on the task allocation problem in transportation systems, and even fewer directly used to allocate tasks, considering the risk of conflicts between agents. In this paper, we propose an option-based RL algorithm with conditioned updating to make agents learn a task allocation policy to complete tasks while preventing conflicts between them. We use a multicar elevator (MCE) system as test application. Simulation results show that with our algorithm, elevator cars in the same shaft effectively learn to respond to service calls without interfering with each other, under different passenger arrival rates, and system configurations.

WSNs (Wireless Sensor Networks) are becoming more widely used in various fields, and localization is a crucial and essential issue for sensor network applications. In this letter, we propose a low-complexity localization mechanism for WSNs that operate in 3D (three-dimensional) space. The basic idea is to use aerial vehicles that are deliberately equipped with anchor nodes. These anchors periodically broadcast beacon signals containing their current locations, and unknown nodes receive these signals as soon as the anchors enter their communication range. We estimate the locations of the unknown nodes based on the proposed scheme that transforms the 3D problem into 2D computations to reduce the complexity of 3D localization. Simulated results show that our approach is an effective scheme for 3D self-positioning in WSNs.

The digital logic rewiring technique has been shown to be one of the most powerful logic transformation methods. It has been proven that rewiring is able to further improve some already excellent results on many EDA problems, ranging from logic minimization, partitioning, FPGA technology mappings to final routings. Previous studies have shown that ATPG-based rewiring is one of the most powerful tools for logic perturbation while a graph-based rewiring engine is able to cover nearly one fifth of the target wires with 50 times runtime speedup. For some problems that only require good-enough and very quick solutions, this new rewiring technique may serve as a useful and more practical alternative. In this work, essential elements in graph-based rewiring such as rewiring patterns, pattern size and locality, etc., have been studied to understand their relationship with rewiring performance. A structural analysis on the target-alternative wire pairs discovered by ATPG-based and graph-based engines has also been conducted to analyze the structural characteristics that favor the identification of alternative wires. We have also developed a hybrid rewiring approach that can take the advantages from both ATPG-based and graph-based rewiring. Experimental results suggest that our hybrid engine is able to achieve about 50% of alternative wire coverage when compared with the state-of-the-art ATPG-based rewiring engine with only 4% of the runtime. Through applying our hybrid rewiring approach to the FGPA technology mapping problem, we could achieve similar depth level and look-up table number reductions with much shorter runtime. This shows that the fast runtime of our hybrid approach does not sacrifice the quality of certain rewiring applications.

A two-dimensional shape is generally represented with line drawings or object contours in a digital image. Shapes can be divided into two types, namely ordered and unordered shapes. An ordered shape is an ordered set of points, while an unordered shape is an unordered set. As a result, each type typically uses different attributes to define the local descriptors involved in representing the local distributions of points sampled from the shape. Throughout this paper, we focus on unordered shapes. Since most local descriptors of unordered shapes are not scale-invariant, we usually make the shapes in an image data set the same size through scale normalization, before applying shape matching procedures. Shapes obtained through scale normalization are suitable for such descriptors if the original whole shapes are similar. However, they are not suitable if parts of each original shape are drawn using different scales. Thus, in this paper, we present a scale-invariant descriptor constructed by von Mises distributions to deal with such shapes. Since this descriptor has the merits of being both scale-invariant and a probability distribution, it does not require scale normalization and can employ an arbitrary measure of probability distributions in matching shape points. In experiments on shape matching and retrieval, we show the effectiveness of our descriptor, compared to several conventional descriptors.

Traditional cellular networks suffer the so-called “cell-edge problem” in which the user throughput is deteriorated because of pathloss and inter-cell (co-channel) interference. Recently, Base Station Cooperation (BSC) was proposed as a solution to the cell-edge problem by alleviating the interference and improving diversity and multiplexing gains at the cell-edge. However, it has minimal impact on cell-inner users and increases the complexity of the network. Moreover, static clustering, which fixes the cooperating cells, suffers from inter-cluster interference at the cluster-edge. In this paper, dynamic fractional cooperation is proposed to realize dynamic clustering in a shared RRU network. In the proposed algorithm, base station cooperation is performed dynamically at cell edges for throughput improvement of users located in these areas. To realize such base station cooperation in large scale cellular networks, coordinated scheduling and distributed dynamic cooperation are introduced. The introduction of coordinated scheduling in BSC multi-user MIMO not only maximizes the performance of BSC for cell-edge users but also reduces computational complexity by performing simple single-cell MIMO for cell-inner users. Furthermore, the proposed dynamic clustering employing shared RRU network realizes efficient transmission at all cell edges by forming cooperative cells dynamically with minimal network complexity. Owing to the combinations of the proposed algorithms, dynamic fractional cooperation achieves high network performance at all areas in the cellular network. Simulation results show that the cell-average and the 5% cell-edge user throughput can be significantly increased in practical cellular network scenarios.

PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, especially when the circuit operation and/or inputs are highly biased. We then devise and evaluate two annotation methods of stress probability to gate-level timing analysis; one guarantees the pessimism desirable for timing analysis and the other aims to obtain the result close to transistor-level timing analysis. Experimental results show that gate-level timing analysis with transistor-level stress probability calculation estimates the increase in delay with 12.6% error.

We propose a capacitive averaging technique applied to a double-tail latched comparator without a preamplifier for an offset reduction technique. Capacitive averaging can be introduced by considering the first stage of the double-tail latched comparator as a capacitive loaded amplifier. This makes it possible to reduce the offset voltage while preventing an increase in power dissipation. A positive feedback technique is also used for the first stage, which maximizes the effectiveness of the capacitive averaging. The capacitive averaging mechanism and the relationship between the offset reduction and the linearity of the amplifier is discussed in detail. Simulation results for a 90-nm CMOS process show that the proposed technique can reduce the offset voltage by 1/3.5 (3 mV) at a power dissipation of only 45 µW.

Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.

Based on the substrate integrated waveguide (SIW) technology, a new type of varactor-tuned radial power divider has been developed with a single bias supply. The varactors are used as tuning elements and allow for a frequency agile behavior. In addition, bandwidth characteristics have been analysed with group-delay. It has been measured with a single bias supply ranging from 6 V to 12 V that the center frequency of the power divider can be adjusted from 6.6 GHz to 7.2 GHz (600 MHz, 11.5%) while maintaining a low insertion loss (< 1 dB) in the passband.

To characterize and predict the dynamics of the nonlinear polarization rotation in SOAs, an experimental method based on the frequency response technique and a model based on the density matrix and effective index formalisms are presented. Both determine the angular displacement, at the Poincare Sphere, that produces the evolution of the polarization of the output signal.

In this paper, we propose a hybrid test application in partial skewed-load (PSL) scan design. The PSL scan design in which some flip-flops (FFs) are controlled as skewed-load FFs and the others are controlled as broad-side FFs was proposed in [1]. We notice that the PSL scan design potentially has a capability of two test application modes: one is the broad-side test mode, and the other is the hybrid test mode which corresponds to the test application considered in [1]. According to this observation, we present a hybrid test application of the two test modes in the PSL scan design. In addition, we also address a way of skewed-load FF selection based on propagation dominance of FFs in order to take advantage of the hybrid test application. Experimental results for ITC'99 benchmark circuits show that the hybrid test application in the proposed PSL scan design can achieve higher fault coverage than the design based on the skewed-load FF selection [1] does.

Current trends in modern out-of-order processors involve implementing deeper pipelines and a large instruction window to achieve high performance, which lead to the penalty of the branch misprediction recovery being a critical factor in overall processor performance. Multi path execution is proposed to reduce this penalty by executing both paths following a branch, simultaneously. However, there are some drawbacks in this mechanism, such as design complexity caused by processing both paths after a branch and performance degradation due to hardware resource competition between two paths. In this paper, we propose a new recovery mechanism, called Recovery Critical Misprediction (RCM), to reduce the penalty of branch misprediction recovery. The mechanism uses a small trace cache to save the decoded instructions from the alternative path following a branch. Then, during the subsequent predictions, the trace cache is accessed. If there is a hit, the processor forks the second path of this branch at the renamed stage so that the design complexity in the fetch stage and decode stage is alleviated. The most contribution of this paper is that our proposed mechanism employs critical path prediction to identify the branches that will be most harmful if mispredicted. Only the critical branch can save its alternative path into the trace cache, which not only increases the usefulness of a limited size of trace cache but also avoids the performance degradation caused by the forked non-critical branch. Experimental results employing SPECint 2000 benchmark show that a processor with our proposed RCM improves IPC value by 10.05% compared with a conventional processor.

Multi-operand adders, which calculates the summation of more than two operands, usually consist of compressor trees which reduce the number of operands to two without any carry propagation, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compressor trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show that the number of GPCs are reduced by up to 22% compared to the existing heuristic. Its effectivity on reduction of delay is also shown against existing approaches on Altera's Stratix III.

The increase in the advanced location based services such as traffic coordination and management necessitates the need for advanced models tracking the positions of Moving Objects (MOs) like vehicles. Due to computer processing limitations, it is impossible for MOs to continuously update their locations. This results in the uncertainty nature of a MO's location between any two reported positions. Efficiently managing and quantifying the uncertainty regions of MOs are needed in order to support different types of queries and to improve query response time. This challenging problem of modeling uncertainty regions associated with MO was recently addressed by researchers and resulted in models that ranged from linear which require few properties of MOs as input to the models, to non-linear that are able to more accurately represent uncertainty regions by considering higher degree input. This paper summarizes and discusses approaches in modeling uncertainty regions associated with MOs. It further illustrates the need for appropriate approximations especially in the case of non-linear models as the uncertainty regions become rather irregularly shaped and difficult to manage. Finally, we demonstrate through several experimental sets the advantage of non-linear models over linear models when the uncertainty regions of MOs are approximated by two different approximations; the Minimum Bounding Box (MBB) and the Tilted Minimum Bounding Box (TMBB).

The proposed scheduling scheme minimizes the energy consumption of a real-time task on the multi-core processor with the dynamic voltage and frequency scaling capability. The scheme allocates a pertinent number of cores to the task execution, inactivates unused cores, and assigns the lowest frequency meeting the deadline. For a periodic real-time task with consecutive real-time instances, the scheme prepares the minimum-energy solutions for all input cases at off-line time, and applies one of the prepared solutions to each real-time instance at runtime.

Wireless sensor networks are comprised of several sensor nodes that communicate via wireless technology. Locating the sensor nodes is a fundamental problem in developing applications for wireless sensor networks. In this paper, we introduce a distributed localization scheme, called the Rectangle Overlapping Approach (ROA), using a mobile beacon with GPS and a directional antenna. The node locations are computed by performing simple operations that rely on the rotation angle and position of the mobile beacon. Simulation results show that the proposed scheme is very efficient and that the node positions can be determined accurately when the beacon follows a random waypoint movement model.

In this paper, we propose an approach to obtaining enhanced performance of the Linpack benchmark on a GPU-accelerated PC cluster connected via relatively slow inter-node connections. For one node with a quad-core Intel Xeon W3520 processor and a NVIDIA Tesla C1060 GPU card, we implement a CPU–GPU parallel double-precision general matrix–matrix multiplication (dgemm) operation, and achieve a performance improvement of 34% compared with the GPU-only case and 64% compared with the CPU-only case. For an entire 16-node cluster, each node of which is the same as the above and is connected with two gigabit Ethernet links, we use a computation-communication overlap scheme with GPU acceleration for the Linpack benchmark, and achieve a performance improvement of 28% compared with the GPU-accelerated high-performance Linpack benchmark (HPL) without overlapping. Our overlap GPU acceleration solution uses overlaps in which the main inter-node communication and data transfer to the GPU device memory are overlapped with the main computation task on the CPU cores. These overlaps use multi-core processors, which almost all of today's high-performance computers use. In particular, as well as using a CPU core for communication tasks, we also simultaneously use other CPU cores and the GPU for computation tasks. In order to enable overlap between inter-node communication and computation tasks, we eliminate their close dependence by breaking the main computation task into smaller tasks and rescheduling. Based on a scheme in which part of the CPU computation power is simultaneously used for tasks other than computation tasks, we experimentally find the optimal computation ratio for CPUs; this ratio differs from the case of parallel dgemm operation of one node.