In multiuser cognitive radio (CR) networks, we address the problem of joint transmit beamforming (BF) and power control (PC) for secondary users (SUs) when they are allowed to transmit simultaneously with primary users (PUs). The objective is to optimize the network sum rate under the interference constraints of PUs, which is a nonconvex problem. Iterative dual subgradient (IDuSuG) algorithm is proposed by iteratively performing BF and PC to optimize the sum rate, among which minimum mean square error (MMSE) or virtual power-weighed projection (VIP2) is used to design beamformers and subgradient method is used to control the power. VIP2 algorithm is devised for the case in which the interference caused by MMSE beamformer exceeds the threshold. Moreover, channel uncertainty due to lack of cooperation is considered. A closed-form worst-case expression is derived, with which the uncertainty optimization problem is transformed into a certain one. A robust algorithm based on IDuSuG is provided by modifying updates in iterative process. Furthermore, second-order cone programming approximation (SOCPA) method is proposed as another robust algorithm. Typical network models are approximated to SOCP problems and solved by interior-point method. Finally the network sum rates for different PU and SU numbers are assessed for both certainty and uncertainty channel models by simulation.

In this paper, a low complexity hybrid smart antenna system with directional elements and reduced-size digital beamformer is proposed to combat the inter-symbol interference (ISI) problem over frequency-selective fading channel. For the conventional smart antenna system with omni-directional elements, it utilizes the full-size digital beamformer to suppress interference and obtain the optimum performance. However, the proposed hybrid smart antenna system with directional elements can be split the linear array receiver for two branches. One branch is the subarray system with non ISI interference, which can be used for maximum ratio combiner (MRC). Another branch is the reduced-size subarray system with the ISI interference, which can use the reduced-size optimum beamformer to suppress interference. Finally, the output signals of the two branches can be combined to detect the transmitted signals. Simulation results confirm that the proposed low complexity system can provide robust performance under the multipath fading channel.

In the near future, interconnection networks of massively parallel computer systems will connect more than a hundred thousands of computing nodes. The performance evaluation of the interconnection networks can provide real insights to help the development of efficient communication library. Hence, to evaluate the performance of such interconnection networks, simulation tools capable of modeling the networks with sufficient details, supporting a user-friendly interface to describe communication patterns, providing the users with enough performance information, completing simulations within a reasonable time, are a real necessity. This paper introduces a novel interconnection network simulator NSIM, for the evaluation of the performance of extreme-scale interconnection networks. The simulator implements a simplified simulation model so as to run faster without any loss of accuracy. Unlike the existing simulators, NSIM is built on the execution-driven simulation approach. The simulator also provides a MPI-compatible programming interface. Thus, the simulator can emulate parallel program execution and correctly simulate point-to-point and collective communications that are dynamically changed by network congestion. The experimental results in this paper showed sufficient accuracy of this simulator by comparing the simulator and the real machine. We also confirmed that the simulator is capable of evaluating ultra large-scale interconnection networks, consumes smaller memory area, and runs faster than the existing simulator. This paper also introduces a simulation service built on a cloud environment. Without installing NSIM, users can simulate interconnection networks with various configurations by using a web browser.

The purpose of this paper is to present the static and dynamic characteristics and a smart design approach for the digital PID control forward type multiple-output dc-dc converter. The central problem of a smart design approach is how to decide the integral coefficient. Since the integral coefficient decision depends on the static characteristics, whatever integral coefficient is selected will not be yield superior dynamic characteristics. Accordingly, it is important to identify the integral coefficient that optimizes static as well as dynamic characteristics. In proposed design approach, it set the upper and lower of input voltage and output current of regulation range. The optimal integral coefficient is decided by the regulation range of the static characteristics and the dynamic characteristics and then the smart design approach is summarized. As a result, the convergence time is improved 50% compared with the conventional designed circuit.

Orthogonal frequency division multiple access (OFDMA) is adopted as a multiuser access scheme in recent cellular systems such as long term evolution (LTE) and WiMAX. In those systems, the performance improvement on cell-edge users is crucial to provide high-speed services. We propose a new resource allocation scheme based on multiple input multiple output – orthogonal frequency division multiple access – code division multiplexing (MIMO-OFDMA-CDM) to achieve performance improvements in terms of cell-edge user throughput, bit error rate, and fairness among users. The proposed scheme adopts code division multiplexing for MIMO-OFDMA and a modified proportional fairness algorithm for CDM, which enables the fairness among users and a higher throughput. The performance improvements are clarified by theoretical analysis and simulations.

A finite buffer shared by multiple packet queues is considered. Partitioning the buffer to maximize total throughput is formulated as a resource allocation problem, the solution is shown to be achieved by a greedy incremental algorithm in polynomial time. The optimal buffer allocation strategy is applied to different models for a wireless downlink. First, a set of parallel M/M/1/mi queues, corresponding to a downlink with orthogonal channels is considered. It is verified that at high load, optimal buffer partitioning can boost the throughput significantly with respect to complete sharing of the buffer. Next, the problem of optimal combined buffer allocation and channel assignment problems are shown to be separable in an outage scenario. Motivated by this observation, buffer allocation is considered in a system where users need to be multiplexed and scheduled based on channel state. It is observed that under finite buffers in the high load regime, scheduling simply with respect to channel state with a simply partitioned buffer achieves comparable throughput to combined channel and queue-aware scheduling.

In this paper, a distributed cooperative multicell beamforming algorithm is proposed, and a detail analysis and solving method for instantaneous and statistical channel state information (CSI) are presented. Firstly, an improved distributed iterative beamforming algorithm is proposed for the multiple-input single-output interference channel (MISO IC) scenario which chooses virtual signal-to-interference-and-noise (SINR) as decision criterion to initialize and then iteratively solves the constrained optimization problem of maximizing the virtual SINR for a given level of generated interference to other users. Then, the algorithm is generalized to the multicell date sharing scenario with a heuristics power allocation scheme based on a viewpoint of the layered channel. Finally, the performance is illustrated through numerical simulations.

In Long-Term Evolution (LTE)-Advanced, a heterogeneous network in which femtocells and picocells overlay macrocells is being extensively discussed in addition to traditional well-planned macrocell deployment to improve further the system throughput. In heterogeneous network deployment, cell selection as well as inter-cell interference coordination (ICIC) is very important to improve the system and cell-edge throughput. Therefore, this paper investigates three cell selection methods associated with ICIC in heterogeneous networks in the LTE-Advanced downlink: Signal-to-interference plus noise power ratio (SINR)-based cell selection, reference signal received power (RSRP)-based cell selection, and reference signal received quality (RSRQ)-based cell selection. The results of simulations (4 picocells and 25 sets of user equipment are uniformly located within 1 macrocell) that assume a full buffer model show that the downlink cell and cell-edge user throughput levels of RSRP-based cell selection are degraded by approximately 2% and 11% compared to those for SINR-based cell selection under the condition of maximizing the cell-edge user throughput due to the impairment of the interference level. Furthermore, it is shown that the downlink cell-edge user throughput of RSRQ-based cell selection is improved by approximately 5%, although overall cell throughput is degraded by approximately 6% compared to that for SINR-based cell selection under the condition of maximizing the cell-edge user throughput.

This work addresses the problem of a fast packet retransmission scheme intended for transporting delay-sensitive flows in a Cooperative Diversity (CD) environment. This cooperative fast retransmission scheme exploits the advantages of the CD environment and hybrid Automatic-Repeat-reQuest (ARQ), while allowing retransmission just one time via a cooperating user (i.e., partner) or via both the sender and the partner simultaneously. Complementary link packets are used for the retransmission whose policy can be adjusted on the basis of the qualities of channels among the sender, the partner and the receiver, as well as the application layer protocol data unit size, using the application throughput as the objective. For this scheme, we first derive the application throughput formulas which are then verified via simulations. Next, the CD-based optimized fast retransmission scheme is shown able to achieve better effective throughput (goodput) than other CD-based or non-CD-based ARQ schemes in various Nakagami-m slow-fading environments. As a result, the proposed scheme should be an excellent fast retransmission mechanism for real-time multimedia transport in many CD environments.

Accurate channel estimation for multiple cells is essential in downlink coordinated multi-point (CoMP) transmission/reception. Therefore, this paper investigates a technique to improve the channel estimation for downlink CoMP in Long-Term Evolution (LTE)-Advanced. In particular, the performance of data signal muting, i.e., muting data signals that collide with the channel state information reference signal (CSI-RS) of a neighboring cell, is evaluated considering various CoMP schemes and intra-eNodeB and inter-eNodeB CoMP scenarios. In a multi-cell link level simulation, coordinated scheduling and coordinated beamforming (CS/CB) CoMP is employed. The simulation results show that data signal muting is effective in improving the channel estimation accuracy, which is confirmed by numerical analysis. Simulation results also show that it is effective in improving the throughput performance, especially for sets of user equipment at the cell boundary. Furthermore, the tradeoff relationship between accurate channel estimation by muting larger numbers of data signals and a high peak data rate, i.e., low overhead, is investigated. It is shown that when the number of coordinated cells is set to three, the CSI-RS reuse factor is set to three, and the well-planned CSI-RS pattern allocation is employed, the improvement in performance is almost saturated in a synchronized network.

This paper investigates a precoding method in downlink multiuser multiple-input multiple-output (MIMO) transmission with multiple base station (BS) cooperation, where each user device basically feeds back the instantaneous channel state information (CSI) to only the nearest BS, but the users near the cell edge additionally feedback the instantaneous CSI to the second nearest BS among the cooperating BSs. Our precoding method is categorized as a form of multi-cell processing (MCP) [5], in which the transmission information to a user is shared by the cooperating BSs in order to utilize fully the degrees of freedom of the spatial channel, and is based on block diagonalization of the channel matrix. However, since some elements of the channel matrix are unknown, we allow partially non-orthogonal transmission. More specifically, we allow inter-user interference to users with limited instantaneous CSI feedback from the channel where the instantaneous CSIs of those users are not obtained at the BSs. The other sources of inter-user interference are set to zero based on the block diagonalization of the channel matrix. The proposed method more efficiently utilizes the degrees of freedom of the spatial channel compared to the case with full orthogonal transmission at the cost of increased inter-user interference. Simulation results show the effectiveness of the proposed method compared to the conventional approaches, which can accommodate the partial CSI feedback scenario, from the viewpoints of the required transmission power and achievable throughput.

This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.

In the Long-Term Evolution (LTE)-Advanced downlink, a user-specific demodulation reference signal (DM-RS) is used to support channel estimation and data demodulation for user-transparent multi-antenna and/or multi-point (MA/P) transmission techniques. A hybrid code division multiplexing (CDM) and frequency division multiplexing (FDM) scheme is adopted as a DM-RS multiplexing scheme for up to eight data streams per user. A time-domain orthogonal cover code (OCC) is used for CDM since time domain orthogonality among OCCs offers good robustness against channel variation. However, in a medium-to-high mobility environment, orthogonality distortion occurs among OCCs, which results in performance degradation. In this paper, we propose a two-dimensional (2D)-OCC mapping that achieves two-dimensional orthogonality in the time and frequency domains to improve the performance of CDM-based DM-RSs while reducing the peak transmission power of the OFDM symbol which includes the DM-RSs. Simulation results show that the proposed 2D-OCC mapping is effective in improving the block error rate performance especially in medium-to-high mobility environments. Furthermore, it is shown that the 2D-OCC mapping effectively reduces the peak power compared to the time-domain OCC mapping.

In off-line analysis, the demand for high precision signal processing has introduced a new method called Empirical Mode Decomposition (EMD), which is used for analyzing a complex set of data. Unfortunately, EMD is highly compute-intensive. In this paper, we show parallel implementation of Empirical Mode Decomposition on a GPU. We propose the use of “partial+total” switching method to increase performance while keeping the precision. We also focused on reducing the computation complexity in the above method from O(N) on a single CPU to O(N/P log (N)) on a GPU. Evaluation results show our single GPU implementation using Tesla C2050 (Fermi architecture) achieves a 29.9x speedup partially, and a 11.8x speedup totally when compared to a single Intel dual core CPU.

PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, especially when the circuit operation and/or inputs are highly biased. We then devise and evaluate two annotation methods of stress probability to gate-level timing analysis; one guarantees the pessimism desirable for timing analysis and the other aims to obtain the result close to transistor-level timing analysis. Experimental results show that gate-level timing analysis with transistor-level stress probability calculation estimates the increase in delay with 12.6% error.

This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.

The digital logic rewiring technique has been shown to be one of the most powerful logic transformation methods. It has been proven that rewiring is able to further improve some already excellent results on many EDA problems, ranging from logic minimization, partitioning, FPGA technology mappings to final routings. Previous studies have shown that ATPG-based rewiring is one of the most powerful tools for logic perturbation while a graph-based rewiring engine is able to cover nearly one fifth of the target wires with 50 times runtime speedup. For some problems that only require good-enough and very quick solutions, this new rewiring technique may serve as a useful and more practical alternative. In this work, essential elements in graph-based rewiring such as rewiring patterns, pattern size and locality, etc., have been studied to understand their relationship with rewiring performance. A structural analysis on the target-alternative wire pairs discovered by ATPG-based and graph-based engines has also been conducted to analyze the structural characteristics that favor the identification of alternative wires. We have also developed a hybrid rewiring approach that can take the advantages from both ATPG-based and graph-based rewiring. Experimental results suggest that our hybrid engine is able to achieve about 50% of alternative wire coverage when compared with the state-of-the-art ATPG-based rewiring engine with only 4% of the runtime. Through applying our hybrid rewiring approach to the FGPA technology mapping problem, we could achieve similar depth level and look-up table number reductions with much shorter runtime. This shows that the fast runtime of our hybrid approach does not sacrifice the quality of certain rewiring applications.

Visibly pushdown automata (VPA), introduced by Alur and Madhusuan in 2004, is a subclass of pushdown automata whose stack behavior is completely determined by the input symbol according to a fixed partition of the input alphabet. Since it was introduced, VPA have been shown to be useful in various contexts, e.g., as specification formalism for verification and as an automaton model for processing XML streams. However, implementation of formal verification based on VPA framework is a challenge. In this paper, we propose on-the-fly algorithms to test universality and inclusion problems of this automata class. In particular, we first present a slight improvement on the upper bound for determinization of VPA. Next, in order to check universality of a nondeterministic VPA, we simultaneously determinize this VPA and apply the P-automata technique to compute a set of reachable configurations of the target determinized VPA. When a rejecting configuration is found, the checking process stops and reports that the original VPA is not universal. Otherwise, if all configurations are accepting, the original VPA is universal. Furthermore, to strengthen the algorithm, we define a partial ordering over transitions of P-automaton, and only minimal transitions are used to incrementally generate the P-automaton. The purpose of this process is to keep the determinization step implicitly for generating reachable configurations as minimum as possible. This improvement helps to reduce not only the size of the P-automaton but also the complexity of the determinization phase. We implement the proposed algorithms in a prototype tool, named VPAchecker. Finally, we conduct experiments on randomly generated VPA. The experimental results show that the proposed method outperforms the standard one by several orders of magnitude.

As an application of the direct sequence spread spectrum (SS) communication system, there is an M-ary bi-orthogonal SS communication system. In its system, several spreading sequences (bi-orthogonal sequences) are used in a code shift keying basis. Hence, design of the spreading code synchronization system has been an issue in the M-ary bi-orthogonal SS systems. In this paper, the authors focus on a code tracking system using a differential detector and a Delay Lock Loop (DLL). They investigate a tracking performance of their code tracking system by theoretical analysis. In addition, a multi-stage interference canceler is applied to the M-ary bi-orthogonal SS system. As the result, it is shown that the tracking performance of the theoretical analysis is almost the same as that of computer simulations in a multi-user environment. It is also shown that the multi-stage interference canceler is effective in improvement of the BER performance.

We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90 different angles. The designs in a 180-nm CMOS process and a 65-nm CMOS process were fabricated to confirm its process scalability; in the respective designs, we observed 36.6% and 38.3% improvements in a power-delay products, compared with the conventional MPOSCs using inverters and nMOS latches. In a 65-nm process, the measured DNL and 3σ period jitter are, respectively, less than 1.22 and 5.82 ps. The power is 284 µW at 1.85 GHz.