A resource allocation scheme for multi-access MIMO-OFDM systems in uplink was developed to improve power and spectrum efficiency in the frequency and the space domains [1]. The scheme requires a multi-user detector in the receiver and assumes identical spatial crosscorrelation across all subcarriers for any pair of spatially separable users. However, the multi-user detection device may not exist in the receiver and the identical spatial crosscorrelation assumption may not be valid in some operational scenarios. The paper develops a scheme to remedy these problems for multi-access MIMO-OFDM systems without using multi-user detection techniques and the assumption. The proposed scheme aims at minimizing the total user transmit power while satisfying the required data rate, the maximum transmit power constraint, and the bit error rate of each user. The simulation results are presented to demonstrate the efficacy of the proposed algorithm.

Duobinary signaling has been introduced into asymmetric multi-chip communications such as DRAM or display interfaces, which allows a controlled amount of ISI to reduce signaling bandwidth by 2/3. A × 2 oversampled equalization has been developed to realize Duobinary signaling. Symbol-rate clock recovery form Duobinary signal has been developed to reduce power consumption for receivers. A Duobinary transmitter test chip was fabricated with 90-nm CMOS process. A 3.5 dB increase in eye height and a 1.5 times increase in eye width was observed.

Power-aware scheduling of periodic tasks in real-time systems has been extensively studied to save energy while still meeting the performance requirement. Many previous studies use the probability information of tasks' execution cycles to assist the scheduling. However, most of these approaches adopt heuristic algorithms to cope with realistic CPU models with discrete frequencies and cannot achieve the globally optimal solution. Sometimes they even show worse results than non-stochastic DVS schemes. This paper presents an optimal DVS scheme for frame-based real-time systems under realistic power models in which the processor provides only a limited number of speeds and no assumption is made on power/frequency relation. A suboptimal DVS scheme is also presented in this paper to work out a solution near enough to the optimal one with only polynomial time expense. Experiment results show that the proposed algorithm can save at most 40% more energy compared with previous ones.

We investigate the problem of switch port allocation in WDM networks that use the hybrid optical-electronic switching node architecture. The objective is to support given traffic demands while minimizing the number of electronic switch ports used, or equivalently minimizing the number of established lightpaths. We first formulate the problem as a mixed integer linear programming (MILP) problem. However, due to the high computational complexity of exact optimization, we develop a simulated annealing (SA) algorithm to get an approximate solution. Results from the SA algorithm demonstrate that, compared to the optical-electrical-optical (O-E-O) node architecture, a WDM network that employs the hybrid switching node architecture requires many fewer lightpaths. We also develop a lightpath assignment heuristic which requires much less computation time than the SA algorithm while maintaining close objective values. The lightpath assignment heuristic is used to investigate the switch port allocation behaviors. Simulation results show that nodes with high degrees or with small average node distances require large numbers of optical switch ports. Moreover, nodes with large amounts of terminate (originated/destined) traffic require large numbers of electronic switch ports. Since the lightpath assignment heuristic requires small computation time, it can be used in the network design process in which a large number of network scenarios must be considered.

In this paper, we present a 0.18-µm CMOS fully integrated X-band shock wave generator (SWG) with an on-chip dipole antenna and a digitally programmable delay circuit (DPDC) for pulse beam-formability in short-range and hand-held microwave active imaging applications. This chip includes a SWG, a 5-bit DPDC and an on-chip wide-band meandering dipole antenna. By using an integrated transformer, output pulse of the SWG is sent to the on-chip meandering dipole antenna. The SWG operates based on damping conditions to produce a 0.4-V peak-to-peak (p-p) pulse amplitude at the antenna input terminals in HSPICE simulation. The DPDC is designed to adjust delays of shock-wave outputs for the purpose of steering beams in antenna array systems. The wide-band dipole antenna element designed in the meandering shape is located in the top metal of a 5-metal-layer 0.18-µm CMOS chip. By simulating in Momentum of ADS 2009, the minimum value of antenna's return loss, S 11, and antenna's bandwidth (BW) are -19.37 dB and 25.3 GHz, respectively. The measured return loss of a stand-alone integrated meandering dipole is from -26 dB to -10 dB with frequency range of 7.5-12 GHz. In measurements of the SWG with the integrated antenna, by using a 20-dB standard gain horn antenna placed at a 38-mm distance from the chip's surface, a 1.1-mVp-p shock wave with a 9-11-GHz frequency response is received. A measured 3-ps pulse delay resolution is also obtained. These results prove that our proposed circuit is suitable for the purpose of fully integrated pulse beam-forming system.

In this paper, we present a numerical method for the equiripple approximation of IIR digital filters. The conventional rational Remez algorithm quickly finds the squared magnitude response of the optimal IIR digital filters, and then by factorizing it the equiripple filter is obtained. Unlike the original Remez algorithm for FIR filters, it is difficult for the rational Remez algorithm to explicitly control the ratio of ripples between different bands. In the conventional lowpass filter design, for example, when different weights are given for its passband and stopband, one needs to iteratively design the filter by manually changing the weights in order to achieve the ratio of the weights exactly. To address this problem, we modify the conventional algorithm and make it possible to directly control the ripple ratio. The method iteratively solves eigenvalue problems with controlling the ripple ratio. Using this method, the equiripple solutions with desired weights are obtained automatically.

We propose a compact matrix-switch-based hierarchical optical cross-connect (HOXC) architecture that effectively handles the colorless waveband add/drop ratio restriction so as to realize switch scale reduction. In order to implement the colorless waveband add/drop function, we develop a wavelength MUX/DMUX that can be commonly used by different wavebands. We prove that the switch scale of the proposed HOXC is much smaller than that of conventional single-layer optical cross-connects (OXCs) and a typical HOXC. Furthermore, we introduce a prototype system based on the proposed architecture that utilizes integrated novel wavelength MUXs/DMUXs. Transmission experiments prove its technical feasibility.

The sensing scheme based on the generalized likelihood ratio test (GLRT) technique has attracted a lot of research interest in the field of cognitive radios (CR). Although its potential advantages in detecting correlated primary signal have been illustrated in prior work, no theoretical analysis of the positive effects of the correlation has appeared in the literature. In this letter, we derive the theoretical false-alarm and detection probabilities of GLRT detector. The theoretical analysis shows that, in the low signal-to-noise ratio (SNR) region, the detector's performance can be improved by exploiting the high correlations between the primary signal samples. The conclusions of the analysis are verified by numerical simulation results.

A method of estimating dual primitives in a textural image is proposed. This method is based on the Primitive, Grain, and Point Configuration (PGPC) texture model, which regards a texture as an arrangement of grains derived from one or a few primitives. Appropriate primitives can be represented by morphological structuring elements estimated from a texture. Conventional primitive estimation methods estimate only one primitive from each textural image. However, they do not work well on textural images that contain more than one basic structure, since two or more types of grain cannot be generated from only one primitive. The proposed method simultaneously estimates two optimal structuring elements of a texture. The experimental results show that the proposed method provides more representative estimations than the conventional method.

This paper creates a new hybrid Space-Time Adaptive Processing (STAP) algorithm that combines Direct Data Domain (D3) method and Space-Time Multiple-Beam (STMB) algorithm, which can effectively suppress discrete interference in the nonhomogeneous clutter environment. In the proposed hybrid algorithm, the D3 method is applied to process the discrete interference in the primary range cell, and the residual clutter is suppressed by the STMB algorithm. The performance of the proposed hybrid STAP algorithm is demonstrated in a simulation.

Linear discriminant analysis (LDA) is one of the well-known schemes for feature extraction and dimensionality reduction of labeled data. Recently, two-dimensional LDA (2DLDA) for matrices such as images has been reformulated into symmetric 2DLDA (S2DLDA), which is solved by an iterative algorithm. In this paper, we propose a non-iterative S2DLDA and experimentally show that the proposed method achieves comparable classification accuracy with the conventional S2DLDA, while the proposed method is computationally more efficient than the conventional S2DLDA.

Tracking a non-rigid object in a video in the presence of background clutter and partial occlusion is challenging. We propose a non-rigid object-tracking paradigm by repeatedly detecting and associating saliency regions. Saliency region segmentation is operated in each frame. The segmentation results provide rich spatial support for tracking and make the reliable tracking of non-rigid object without drifting possible. The precise object region is obtained simultaneously by associating the saliency region using two independent observers. Our formulation is quite general and other salient-region segmentation algorithms also can be used. Experimental results have shown that such a paradigm can effectively handle tracking problems of objects with rapid movement, rotation and partial occlusion.

The influence of quantization scaling is seldom considered in narrow band (NB) communications, because a high resolution analogue-to-digital converter (ADC) can be generally employed. In ultra-wideband (UWB) systems, however, the resolution of ADC is required to be low to reduce complexity, cost and power consumption. Consequently, the influence of quantization scaling is significant and should be taken into account. In this letter, effects of quantization scaling are analyzed in terms of signal to noise ratio (SNR) loss based on an uniformly distributed random signal model. For the effects of quantization scaling on bit error rate (BER) performance, however, theoretical analysis is too complicated since quantization is a nonlinear operation, hence we employ here a simulation method. The simulation results show there exists an optimum scaling to minimize BER performance for a fixed-resolution receiver; the optimum scaling power is related to the SNR of input noisy signal and the resolution of ADC.

As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10-12) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [1] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.

On uniformly convex real Banach spaces, a fixed point theorem in weak topology for successively recurrent system of fuzzy-set-valued nonlinear mapping equations and its application to ring nonlinear network systems are theoretically discussed in detail. An arbitrarily-level likelihood signal estimation is then established.

In this paper, we present a new frequency identification technique using the recent methodology of compressive sensing and discrete prolate spheroidal sequences with optimal energy concentration. Using the bandpass form of discrete prolate spheroidal sequences as basis matrix in compressive sensing, compressive frequency sensing algorithm is presented. Simulation results are given to present the effectiveness of the proposed technique for application to detection of carrier-frequency type signal and recognition of wideband signal in communication.

This paper discusses a dual-stage detection scheme composed of coarse detection stage and refined detection stage for the continuous detection operation of Ultra-Wideband (UWB) detect and avoid (DAA). The threshold factor for the probability of indefinite detection is first proposed and defined to combine the two stages. The proposed scheme focuses on the integration of two different detection schemes with different complexities in order to reduce total computational complexity. A Single-carrier Frequency Division Multiple Access (SC-FDMA) uplink system operating in a Time Division Duplex (TDD) mode is utilized to evaluate the proposed detection scheme. Simulation results indicate that the proposed scheme can make a tradeoff between the detection performance and the computational complexity by setting the probability of indefinite detection.

In this letter a simplified Jury's table for real polynomials is extended to complex polynomials. Then it is shown that the extended table contains information on the root distribution of complex polynomials with respect to the unit circle in the complex plane. The result given in this letter is distinct from the recent one in that root counting is performed in a different way.

Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.