The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] Al(20498hit)

14161-14180hit(20498hit)

  • Fair Queueing Algorithm Using Channel Status Information in an Integrated CDMA System

    Seung Sik CHOI  Dong Ho CHO  

     
    LETTER-Wireless Communication Technology

      Vol:
    E86-B No:5
      Page(s):
    1694-1697

    A Fair Queueing Algorithm is proposed for data services in an integrated voice/data CDMA system. We introduce short-term and long-term fairness concepts to allocate data users fairly. Using these concepts, we propose a Weighted Fair Queueing with Status Control (WFQS) in the consideration of a Generalized Processor Sharing (GPS) fluid-flow model. This proposed scheme allocates resources using channel status information. The throughput and delay of data users could be improved when this scheme is applied to wireless channels.

  • Calibration Method by Image Registration with Synthetic Image of 3D Model

    Toru TAMAKI  Masanobu YAMAMOTO  

     
    LETTER-Image Processing, Image Pattern Recognition

      Vol:
    E86-D No:5
      Page(s):
    981-985

    We propose a method for camera calibration based on image registration. This method registers two images; one is a real image captured by a camera with a calibration object with known shape and texture, and the other is a synthetic image containing the object. The proposed method estimates the parameters of the rotation and translation of the object by using the depth information of the synthetic image. The Gauss-Newton method is used to minimize the residuals of intensities of the two images. The proposed method does not depend on initial values of the minimization, and is applicable to images with much noise. Experimental results using real images demonstrate the robustness against initial state and noise on the image.

  • A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

    Nozomu TOGAWA  Takao TOTSUKA  Tatsuhiko WAKUI  Masao YANAGISAWA  Tatsuo OHTSUKI  

     
    PAPER

      Vol:
    E86-A No:5
      Page(s):
    1082-1092

    Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.

  • Polyhedral Proof of a Characterization of Perfect Bidirected Graphs

    Yoshiko T. IKEBE  Akihisa TAMURA  

     
    PAPER

      Vol:
    E86-A No:5
      Page(s):
    1000-1007

    Bidirected graphs which are generalizations of undirected graphs, have three types of edges: (+,+)-edges, (-,-)-edges and (+,-)-edges. Undirected graphs are regarded as bidirected graphs whose edges are all of type (+,+). The notion of perfection of undirected graphs can be naturally extended to bidirected graphs in terms of polytopes. The fact that a bidirected graph is perfect if and only if the undirected graph obtained by replacing all edges to (+,+) is perfect was independently proved by several researchers. This paper gives a polyhedral proof of the fact and introduces some new knowledge on perfect bidirected graphs.

  • Scalability of Full-Mesh WDM AWG-STAR Network

    Kazuto NOGUCHI  

     
    INVITED PAPER-OECC Awarded Paper

      Vol:
    E86-B No:5
      Page(s):
    1493-1497

    This paper describes the scalability of a full-mesh wavelength division multiplexing star-structure network based on an arrayed-waveguide grating router (AWG-STAR). The scalability of the network is examined experimentally. A power penalty of 0.1dB is obtained with a 32-node network and an estimated scalability of up to 100 nodes is confirmed.

  • Development of an Internet Server System for Personal Live-Broadcasting

    Sangmoon LEE  Sinjun KANG  Byungseok MIN  Hagbae KIM  

     
    PAPER-Broadcast Systems

      Vol:
    E86-B No:5
      Page(s):
    1673-1678

    In this paper, we present an Internet personal live-broadcasting server system. Our solution is not only for experts but also for amateur users who want to broadcast using simple multimedia equipment. For scalable broadcasting services, we developed multiple-channel establishment and channel expansion. Concurrent services for a large number of broadcasting channels are effectively provided. Also, the capacity of channels can be expanded as the number of participants increases. Furthermore, for the sake of complete live broadcasting with high-quality transmission, the system supports both TCP (transmission control protocol) and UDP (user datagram protocol) according to the status of network environments as well as the received packet loss in the user system. The performance of the system is effectively evaluated at such practical commercial sites as well-known community and E-business sites.

  • A Beam Switching Slot Array with a 4-Way Butler Matrix Installed in Single Layer Post-Wall Waveguides

    Shin-ichi YAMAMOTO  Jiro HIROKAWA  Makoto ANDO  

     
    PAPER-Antenna and Propagation

      Vol:
    E86-B No:5
      Page(s):
    1653-1659

    The authors proposed a switching beam slot array antenna with a 4-way Butler matrix. All are integrated in one substrate with post-wall waveguide techniques. The planar Butler matrix is realized by using short slot directional couplers (cross coupler). Experiments in 26GHz band confirmed the key operation of this antenna; almost identical four beams are switched to cover the total of horizontal 90-degree sector with equal angular spacing.

  • New Security Index for Digital Fingerprinting and Its Bounds

    Shingo ORIHARA  Takaaki MIZUKI  Takao NISHIZEKI  

     
    PAPER

      Vol:
    E86-A No:5
      Page(s):
    1156-1163

    Fingerprinting is one of the digital watermarking techniques, and is becoming more important as a copyright protection technique. Fingerprinting must resist collusion attacks. As a security index, "c-secureness" has been proposed, but it has been known that there is indeed no c-secure code. In this paper, we introduce a new index to measure the resilience of fingerprinting for collusion attacks and obtain some upper bounds and a lower bound on the index.

  • Proposal and Preliminary Experiments of Indoor Optical Wireless LAN Based on a CMOS Image Sensor with a High-Speed Readout Function Enabling a Low-Power Compact Module with Large Uplink Capacity

    Keiichiro KAGAWA  Tomohiro NISHIMURA  Takao HIRAI  Yasushi YAMASAKI  Hiroaki ASAZU  Tomoaki KAWAKAMI  Jun OHTA  Masahiro NUNOSHITA  Kunihiro WATANABE  

     
    PAPER

      Vol:
    E86-B No:5
      Page(s):
    1498-1507

    We propose a new scheme of indoor optical wireless LAN based on a special CMOS image sensor (CIS), which realizes a low-power compact communication module with large uplink capacity due to space division multiple access. In our scheme, all nodes and a hub utilize the CIS as a photoreceiver as well as a position-sensing device for finding the positions of the communication modules, while a single large photodiode is used in the conventional systems. Although conventional image sensors cannot detect modulated signals because they integrate photocurrents, our CIS has a high-speed readout function for receiving optical data from the specific pixels receiving optical signals. The advantages of the proposed scheme are 1) compact embodiment of the communication module due to no need of the bulky mechanical components for searching the other modules, 2) space division multiple access, which leads to 3) large capacity of uplink, and 4) applicability of simple modulation and coding schemes for optical signals. In our scheme, diffusive and narrow beam lights are complementally used for position detection and communication, respectively, which leads to the advantage 5) low power consumption of both light emitter and receiver circuits. To demonstrate two basic functional modes of our CIS: an IS (image sensor) mode and a COM (communication) mode, we fabricate an 88-pixel CIS by use of a 0.8µm BiCMOS technology. In the experiments, the image of a light source is successfully captured in the IS mode for integration time of 29.6msec and optical power of 1.1nW. After the functional mode of the pixel receiving the light is changed to the COM mode, the eye pattern of the modulated light is obtained from the pixel at frequency of 1MHz. We also fabricate a test pixel circuit with in-pixel amplifier, with which operation speed is improved to 100MHz.

  • Modification of New Carbon Based Nano-Materials for Field Emission Devices

    Chia-Fu CHEN  Chia-Lun TSAI  

     
    PAPER

      Vol:
    E86-C No:5
      Page(s):
    803-810

    Field emission display (FED) is evolving as a promising technique of flat panel displays in the future. In this paper, various carbon based nanostructures are acted as cathode materials for field emission devices. Dendrite-like diamond-like carbon emitters, carbon nanotubes, carbon nanotips are synthesized by microwave plasma chemical vapor deposition. Many factors affect the performance of field emitters, such as the shape, work function and aspect ratio of emission materials. Modified process of carbon based nano-materials for enhancing field emission efficiency are included intrinsic and extrinsic process. These reformations contain the p-type and n-type doping, carburization and new ultra well-aligned carbon nano-materials. It is found that carbon nano-materials grown on micropatterned diode show higher efficiency of FED. In addition, to achieve a low- turn-on field, the novel scheme involving a new fabrication process of gated structure metal-insulator-semiconductor (MIS) diode by IC technology is also presented.

  • Human Face Extraction and Recognition Using Radial Basis Function Networks

    Kiminori SATO  Nan HE  Yukitoshi TAKAHASHI  

     
    PAPER-Image Processing, Image Pattern Recognition

      Vol:
    E86-D No:5
      Page(s):
    956-963

    Partial face images, e.g., eyes, nose, and ear images are significant for face recognition. In this paper, we present a method for partial face extraction and recognition based on Radial Basis Function (RBF) networks. Focus has been centered on using ear images because they are not influenced by facial expression, and the influences of aging are negligible. Original human side face image with 320240 pixels is input, and then the RBF network locates the ear and extracts it with a 200120 pixel image. Next, another RBF network is constructed for the purpose of recognition. An algorithm that determines the radius of an RBF function is proposed. Dynamic radius, so called as compared to static one, is found through the algorithm that makes RBF functions adaptable to the training samples. We built a database that contains 600 side face images, from 100 people, to test the method and the results of both extraction and recognition are satisfied.

  • Measurement of Fiber Chromatic Dispersion Using a Mode-Locked Fiber Laser

    Shinji YAMASHITA  Rie HAYASHI  

     
    PAPER-Lasers, Quantum Electronics

      Vol:
    E86-C No:5
      Page(s):
    838-841

    We demonstrate a mode-locked fiber laser (MLFL) method for measuring the chromatic dispersion of long transmission fiber. In this method, device under test (DUT) is inserted in the laser cavity, and the chromatic dispersion is measured by the shift of mode-locking frequency when the lasing wavelength is changed. The experimental results of the MLFL method for a 5km-long single-mode fiber had good agreement with the conventional phase-shift method.

  • Time-Memory Trade-off Cryptanalysis for Limited Key on FPGA-Based Parallel Machine RASH

    Katsumi TAKAHASHI  Hiroai ASAMI  Katsuto NAKAJIMA  Masahiro IIDA  

     
    PAPER

      Vol:
    E86-D No:5
      Page(s):
    781-788

    We designed an FPGA-based parallel machine called "RASH"(Reconfigurable Architecture based on Scalable Hardware) for high speed and flexible signal/data processing. Cryptanalysis is one of the killer applications for FPGA-based machines because huge amounts of logical and/or simple arithmetic operations are required and FPGA is suitable for this. One of the well-known activities in cryptanalysis is the DES (Data Encryption Standard) cracking contest conducted by RSA Data Security. TMTO (Time-Memory Trade-Off) Cryptanalysis is a practical method to dramatically shorten the time for key search when plaintext is given in advance. A string of ASCII characters is used as the key much like a password. The ASCII character is 7-bit character and is changed to 96 kinds of value. The 56-bit DES key is given with a string of 8 ASCII characters. Although the DES key has 64 trillion(=256) possibilities, the key that is given with a string has only 6.4 trillion(=968) possibilities. Therefore, we improve TMTO cryptanalysis so that we search only the limited key by ASCII characters and reduce the quantity of computation. In this paper, we demonstrate how TMTO cryptanalysis for limited key is well suited to our FPGA-based RASH machine. By limiting the key to a string, DES key will be found at 80% probability within 45 minutes after ciphertext is given on 10 units of RASH. The precomputation before starting key search takes 3 weeks on the same RASH configuration.

  • An Evolvable Hardware Chip for a Prosthetic-Hand Controller--New Reconfigurable Hardware Paradigm--

    Isamu KAJITANI  Masaya IWATA  Nobuyuki OTSU  Tetsuya HIGUCHI  

     
    PAPER

      Vol:
    E86-D No:5
      Page(s):
    882-890

    This paper presents a new reconfigurable hardware paradigm, called evolvable hardware (EHW), and its application to the biomedical engineering problem of an artificial hand controller. Evolvable hardware is based on the idea of combining a reconfigurable hardware device with an artificial intelligence robust search technique called genetic algorithms (GAs) to execute reconfiguration autonomously. The first version of the EHW chip was designed in 1998, and this paper describes the latest improvements to the EHW chip, as well as outlining its architecture and the hardware implementation of the GA operations. Execution speed for genetic operations is shown to be about 38.7 times faster with the hardware implementation than with software program running on an AMD Athlon processor (1.2GHz). As an application of the EHW chip, this paper introduces a controller for a multi-functional prosthetic-hand, and presents experimental data in which a practical myoelectric pattern classification rate of 97.8% was achieved through the application of the EHW chip.

  • Analysis of XGM-Based Wavelength-Conversion Using ASE in SOAs

    Kenichiro TSUJI  Naoyuki MATSUSHITA  Noriaki ONODERA  Masatoshi SARUWATARI  

     
    PAPER

      Vol:
    E86-C No:5
      Page(s):
    741-748

    Wavelength conversion using the cross-gain modulation (XGM) of amplified spontaneous emission (ASE) in a traveling-wave type semiconductor optical amplifier (TW-SOA) is theoretically studied. Taking into account the spatial and temporal variations of carrier density along the SOA length, output signal and converted ASE waveforms are analyzed. We also reveal the dependency of the signal and converted ASE waveforms on input signal power and repetition frequency, and confirm that numerical analyses well agree with the experimental results. Finally we qualitatively clarify the way to improve frequency response by simulating eye-diagrams for long SOAs and assist light pumping for the first time.

  • An Incremental Wiring Algorithm for VLSI Layout Design

    Yukiko KUBO  Shigetoshi NAKATAKE  Yoji KAJITANI  Masahiro KAWAKITA  

     
    LETTER

      Vol:
    E86-A No:5
      Page(s):
    1203-1206

    One of the difficulties in routing problem is in wirability which is to guarantee a physical connection of a given topological route. Wirability often fails since the width of a wire is relatively large compared with the size of modules. As a possible solution, this paper proposes an incremental wiring algorithm which generates wires net-by-net without overlapping other pre-placed circuit elements. The idea is to divide a wire into a series of rectangles and handles them as modules with additional constraints to keep the shape of the wire. The algorithm was implemented and experimented on a small instance to show its promising performance.

  • A Versatile CMOS Analog Multiplier

    Ittipong CHAISAYUN  Kobchai DEJHAN  

     
    PAPER-Analog Signal Processing

      Vol:
    E86-A No:5
      Page(s):
    1225-1232

    This paper describes a novel four-quadrant analog multiplier. It is comprised of two mixed signal circuits, a voltage adder circuit, a voltage divider circuit and a basic multiplier. Its major advantages over the other analog multipliers are: this design has single ended inputs, the geometry of all CMOS transistors are equal, and its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects are analyzed, and the experimental and simulative results that confirm the theoretical analysis are carried out.

  • A New Analog Correlator Circuit for DS-CDMA Wireless Applications

    Mostafa A. R. ELTOKHY  Boon-Keat TAN  Toshimasa MATSUOKA  Kenji TANIGUCHI  

     
    PAPER-Spread Spectrum Technologies and Applications

      Vol:
    E86-A No:5
      Page(s):
    1294-1301

    A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm 245µm is estimated to be 9 times smaller compared to other reported equivalent analog correlators.

  • Automatic Feature Extraction from Breast Tumor Images Using Artificial Organisms

    Hironori OKII  Takashi UOZUMI  Koichi ONO  Hong YAN  

     
    PAPER-Medical Engineering

      Vol:
    E86-D No:5
      Page(s):
    964-975

    In this paper, we propose a new computer-aided diagnosis system which can extract specific features from hematoxylin and eosin (HE)-stained breast tumor images and evaluate the type of tumor using artificial organisms. The gene of the artificial organisms is defined by three kinds of texture features, which can evaluate the specific features of the tumor region in the image. The artificial organisms move around in the image and investigate their environmental conditions during the searching process. When the target pixel is regarded as a tumor region, the organism obtains energy and produces offspring; organisms in other regions lose energy and die. The searching process is iterated until the 30th generation; as a result, tumor regions are filled with artificial organisms. Whether the detected tumor is benign or malignant is evaluated based on the combination of selected genes. The method developed was applied to 27 test cases and the distinction between benign and malignant tumors by the artificial organisms was successful in about 90% of tumor images. In this diagnosis support system, the combination of genes, which represents specific features of detected tumor region, is selected automatically for each tumor image during the searching process.

  • Coordinated Resource Allocation Scheme in the Forward Link of Sectorized CDMA Systems

    Seung Sik CHOI  Dong Ho CHO  

     
    LETTER-Wireless Communication Technology

      Vol:
    E86-B No:5
      Page(s):
    1689-1693

    We propose a coordinated resource allocation (CRA) scheme that can be used to allocate high data-rate users in sectorized cells. This scheme is useful for allocating high data-rate users at cell boundaries. In order to analyze the performance of the proposed scheme, we make an interference model for a sectorized CDMA system and suggest the system load measurement of the forward link. Based on this system load measurement, data throughput for the CDMA system under perfect and imperfect power control is then analyzed. Numerical results show that throughput is significantly increased when the CRA scheme is used.

14161-14180hit(20498hit)