We have developed a novel self-alignment process using the surface tension of the liquid resin for assembly of electronic or optoelectronic devices. Though the liquid resins have a characteristics as low as one tenth of the surface tension of solder in general, restoring forces for self-alignment capability can be produced by making it constrained on the 3-dimensional pads on chip and substrate. In this paper, its principle and characteristics are described and the relationship between process parameters and joint geometry were examined. And the possibility of self-alignment process was verified by analytic numerical method and scaled-up experiment. A self-alignment accuracy was examined experimentally and show that it became less than 0.4 µm. It can provide a useful information on various parameters involved in joint geometry and optimal design guideline to generate the proper profiles.

In an optical fiber ring topology network such as FDDI (Fiber Distributed Data Interface) rings and SONET (Synchronous Optical Network) rings, the number of consecutively bypassed failed stations is limited by the optical power loss constraint. In recent years, this situation was represented as a consecutive k-out-of-n:F system and the two-terminal reliability was presented in the literature, but K-terminal reliability has not been presented. In this paper, we obtain K-terminal reliability expressions for dual-counter rotating networks (DR's) that use both self-heal and station-bypass switches in which all components (stations, links and bypass switches) can fail. The results are useful in evaluating the reliabilities of FDDI ring networks parametrically and making reliability comparisons. This method can be used to obtain a closed-form reliability expression in a more general ring-network such as 'ring of trees. '

We have manufactured a trial 'Digital Packet Video (PV) Link' system for super high-resolution display. 'Digital PV Link' is a new data transmission protocol where the host transfers video data with attributes for only a selected area such as a motion picture window. This protocol handles the video data with an ID, which can be used for handling between plural hosts and plural displays such as multi display. This ID also makes the display to handle plural windows in accordance with different parameter such as scaling factor, color-adjust, and so on. In this protocol, error handling is a key because the video data is transferred only when the host wants to change display data. So, we have examined transmission errors and capability for motion pictures by using this trial system. In this report, we will introduce the concept and the characteristics of 'Digital PV Link,' and the result of examination.

In this paper we propose a MIN (Multistage Interconnection Network) whose performance in the faulty case degrades as gracefully as possible. We focus on a two-dilated baseline network as a sort of MIN. The link connection pattern in our MIN is determined so that all the available paths established between an input terminal and an output terminal via an identical input of a SE (Switching Element) in some stage will never pass through an identical SE in the next stage. Extra links are useful in improving the performance of the MIN and do not complicate the routing scheme. There is no difference between our MIN and others constructed from a baseline network with regard to numbers of links and cross points in all SEs. The theoretical computation and simulation-based study show that our MIN is superior to others in performance, especially in robustness against concentrated SE faults in an identical stage.

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.

Signal fading due to multipath propagation severely impairs the performance of high speed mobile communication systems. The probability density function (PDF) for the envelope of the received signal using STTD (Space Time Transmitter Diversity) over correlated Nakagami fading channels with additive white Gaussian noise (AWGN) is derived in this paper. System performances of noncoherent signals over slow and flat fading channels in the presence of AWGN can be evaluated from this new PDF.

This paper presents an enhancement of a software project simulator to perform risk prediction with cost estimation capability. So far, we have developed a software project simulator to simulate software development projects. In this simulator, a development process was described using Petri net model, and it was applied to some actual project data in a certain company successfully. On the other hand, we have also presented a risk predicting system to find "risky" projects by statistical analysis on risk questionnaire for project managers. In this approach, only the probability to be risky was calculated for a project. Thus, the managers in the company wanted to know a concrete proof why a software project becomes risky. In this paper, to present the proof that a software project becomes risky, we try to enhance the previous project simulator so that the simulator can deal with risk factors. To consider the risk factors, we modify the previous simulator so that both the fluctuation of skill level and the deadline pressure can be represented by the parameters in the simulator. By using a case study, we confirm that the enhanced simulator can estimate the development cost under some typical risks. As a result, we can expect that the simulator shows how much the development cost of a risky project exceeds an estimate.

In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.

First, we give a graph-theoretic formalization for the spare assignment problems for two cases of reconfiguring NN mesh-connected processor arrays with spares on a diagonal line in the array or two orthogonal lines at the edges of the array. Second, we discuss the problems for minimizing the numbers of "dangerous processors" for the cases. Here, a dangerous processor is a nonfaulty one for which there remains no spare processor to be assigned if it becomes faulty, without modifying the spare assignments to other faulty processors. The problem for the latter case, originally presented by Melhem, has already been discussed and solved by the O(N2) algorithm in [3], but it's procedure is very complicated. Using the above graph-theoretic formalization, we give efficient plain algorithms for minimizing the numbers of dangerous processors by which the problems for both the cases can be solved in O(N) time.

We present an algorithm for computing the Minkowski sum of two surfaces of revolution with parallel axes, each defined as a rotational sweep of a slope-monotone closed curve. This result is an extension of that due to Sugihara et al., where the Minkowski sum for two slope-monotone closed curves in the plane is defined.

A plasma display panel (PDP) represents gray levels by the pulse number modulation technique that results in undesirable dynamic false contours on moving images. Among the various techniques proposed for the reduction of dynamic false contours, the optimization of the subfield pattern can be most easily implemented without the need for any additional dedicated hardware or software. In this paper, a systematic method for selecting the optimum subfield pattern is presented. In the proposed method, a subfield pattern that minimizes the quantitative measure of the dynamic false contour on the predefined test image is selected as the optimum pattern. The selection is made by repetitive calculations based on a genetic algorithm. Quantitative measure of the dynamic false contour calculated by simulation on the test image serves as a criterion for minimization by the genetic algorithm. In order to utilize the genetic algorithm, a structure of a string is proposed to satisfy the requirements for the subfield pattern. Also, three genetic operators for optimization, reproduction, crossover, and mutation, are specially designed for the selection of the optimum subfield pattern.

A distributed network management system (NMS) is urgently needed to manage large number of network managed objects (MOs) such as public network MOs. The ATM Forum has proposed the M4-interface to achieve just such a distributed NMS. However, the basis of the M4-interface is not adequate in terms of flexible distribution, because its main unit of distribution is location. To improve the granularity of the distribution, we have defined the route as a further unit of distribution. We also describe new MOs that provide for a distribution based on routes. A more detailed distribution is then possible than with a distribution purely based on location. In addition, we propose a new CMIP Action to move MOs from one sub-NMS (SubNMS) to another while the system is running. Using this Action, we can achieve a more flexible distribution in terms of network problems and load.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.

An advanced spare-connection scheme for K-out-of-N redundancy is proposed for constructing fault-tolerant ring- or toroidal mesh-connected processing-node arrays able to enhance emulation of binary hypercubes by using bypass networks. With this scheme, a component redundancy configuration for a base array with a fixed number of primary nodes, such as that for 8-node ring or 32-node toroidal mesh, can be constructed by using bypass links with a segmented bus structure to selectively connect the primary nodes to a spare node in parallel. These bypass links are allocated to the primary nodes by graph-node coloring with a minimum inter-node distance of three in order to use the bypass links as the hypercube connections as well as to attain strong fault tolerance for reconfiguring the base array with the primary network topology. An extended redundancy configuration for a large fault-tolerant array can be constructed by connecting the component configurations by using external switches of a hub type provided at the bus nodes of the bypass links. This configuration has a network topology of the parallel star-connections of sub-hypercubes whose diameter is smaller than that of the regular hypercube.

This paper describes agent technology and the various ways in which it can be applied to command, control, communications and intelligence in general, and to network-centric warfare in particular. The paper provides a brief overview of agents, their properties, and their advantages. It covers the concept of the current military trend, network-centric warfare. Problems associated with agents are described, including the conflict between security and autonomy, in a distributed environment. The paper concludes with a discussion of research trends in mobile agents, particularly with regard to applications in the Department of Defense.

A high assurance on-line recovery technology for a space on-board computer that can be realized using commercial devices is proposed whereby a faulty processor node confirms its normality and then recovers without affecting the other processor nodes in operation. Also, the result of an evaluation test using the breadboard model implementing this technology is reported. Because this technology enables simple and assured recovery of a faulty processor node regardless of its degree of redundancy, it can be applied to various applications, such as a launch vehicle, a satellite, and a reusable launch vehicle. As a result, decreasing the cost of an on-board computer is possible while maintaining its high reliability.

Today, people want highly-customized products to satisfy their individual requirements. However traditional manufacturing technology is not geared towards high-mix, low-volume manufacturing. Holonic Manufacturing Systems (HMS) is a new paradigm to bridge this divide. HMS offers enterprises a new breed of technology to continuously reconfigure themselves to manufacture a larger variety of products in smaller batch sizes, and do this profitably. A suitable metaphor for implementing the holonic manufacturing system is the emerging IEC function block architecture. The paper describes how function blocks can be used to build such holonic manufacturing systems. We also illustrate the merits of our approach through a real-world engine assembly line being developed by DaimlerChrysler.

Although research into multimodal interfaces has been around for a long time, we believe that some basic issues have not been studied yet, e.g. the choice of modalities and their combinations is usually made without any quantitative evaluation. This study seeks to identify the best combinations of modalities through usability testing. How do users choose different interaction modes when they work on a particular application? Two experimental evaluations were conducted to compare interaction modes on a CAD system and a map system respectively. For the CAD system, the results show that, in terms of total manipulation time (drawing and modification time) and subjective preferences, the "pen + speech + mouse" combination was the best of the seven interaction modes tested. On the map system, the results show that the "pen + speech" combination mode is the best of fourteen interaction modes tested. The experiments also provide information on how users adapt to each interaction mode and the ease with which they are able to use these modes.

In this paper, two efficient codebook searching algorithms for vector quantization (VQ) are presented. The first fast search algorithm utilizes the compactness property of signal energy of orthogonal transformation. On the transformed domain, the algorithm uses geometrical relations between the input vector and codeword to discard many unlikely codewords. The second algorithm, which transforms principal components only, is proposed to alleviate some calculation overhead and the amount of storage. The relation between the principal components and the input vector is utilized in the second algorithm. Since both of the proposed algorithms reject those codewords that are impossible to be the nearest codeword, they produce the same output as conventional full search algorithm. Simulation results confirm the effectiveness of the proposed algorithms.

This paper proposes a precise method of realizing simultaneous measurement of microscopic defects and the macroscopic three-dimensional shapes of planar objects having specular reflection surfaces. The direction vector field of surface tilt is evaluated directly by the introduction of a moving slit-light technique based on computer graphic animation. A reflected image created by the moving slit-light is captured by a video camera, and the image sequence of the slit-light deformation is analyzed. The obtained direction vector field of the surface tilt recovers the surface shape by means of integration. Two sample objects, a concave mirror and a plane plastic injection molding, are tested to measure the performance of the proposed method. Surface anomalies such as surface dent and warpage are detected quantitatively at a high resolution (about 0.2 [µm]) and a high accuracy (about 95%) in a wide area (about 15 [cm]) of the test object.