In this paper, we investigate the performance of Fast Reservation Protocols (FRP) for burst-level bandwidth allocation in ATM networks. FRP schemes can be classified into delayed transmission (DT) and immediate transmission (IT) methods according to reservation procedure. Moreover, according to the responsibility for negative acknowledgment (NAK) cell generations when burst blocking occurs, FRP schemes can be further classified into blocking node NAK (BNAK) and destination node NAK (DNAK) schemes. We analize the FRP schemes with different reservation and NAK methods for single node and multihop network models, respectively. We then discuss the dependence of performance for each FRP scheme on propagation delay, peak rate, and the number of hops.

It is well known that based on the structure of a transversal filter, the RLS equaliser provides the fastest convergence in stationary environments. This paper addresses an adaptive transversal equaliser which has the potential to provide more faster convergence than the RLS equaliser. A comparison is made with respect to computational complexity required for each update of equaliser coefficients, and computer simulations are demonstrated to show the superiority of the proposed equaliser.

This paper investigates the asymptotic error rate behaviour for noncoherent OOK signalling scheme in the presence of Nakagami-m fading. A transcendental equation to compute the optimum threshold level is also derived. Comparison on trends in optimum threshold level and its corresponding ratio of the Mark and Space error probabilities between different channels are presented.

While spatial reuse in a high-speed ring increases the throughput performance, it leads to a fairness problem in distributing the network bandwidth among distinct nodes. To alleviate this problem, fairness control algorithms based on a packet window have been developed. Under these algorithms, satisfied nodes are forced to pass empty slots to starved downstream nodes until their windows are refilled by a reset signal. This regulation incurs a bandwidth waste corresponding to the travel distance of those empty slots. In this paper, a waste-free fairness control method based on a two-layer window composed of the cycle and packet windows is developed. Using the proposed method, packets allocated to multiple fairness cycles are simultaneously transferred and, in consequence, the otherwise wasted bandwidth can be reused to carry, in advance, packets allocated to future fairness cycles. This method is applied to two typical ring protocols with only the packet window, ATMR and MetaRing, and their performances are investigated. The simulation results show that the cycle window is very effective to improve the performance of the ATMR and MetaRing protocols.

This paper presents adaptive image enhancement algorithms which enhance hidden signals in the pictures and describes their implementation for real-time video signals. An image enhancement algorithm proposed by T. Peli and J. S. Lim is extended for application to video signals. A fast implementation algorithm is provided with parallel implementation. The proposed algorithms are shown to be realized in real-time on 200 MHz microprocessors with multimedia extensions for 720 480 (pixels) 30 frames/sec video signals.

Orthogonal Multi-Carrier-Code Division Multiple Access (OMC-CDMA) is a scheme that combines multi-carrier modulation with Direct Sequence Spread Spectrum (DS-SS) and allows the efficient utilization of the bandwidth, the resistance against frequency selective fading in broadband mobile radio channels and the efficient implementation by the FFT algorithm. In this paper, we analyze the bit error probability (BER) of OMC-CDMA on two-ray Rayleigh multipath fading channels with the delay time and compare the BER performances of OMC-CDMA according to the number of users (M) and subcarriers (N), and the power of delayed path. We found that the performance of OMC-CDMA depends greatly on the power of delayed signal. If the power of delayed signal is increased from 10% to 50% as compared with the direct path power, the capacity of OMC-CDMA is decreased approximately by 40% at BER=10-3, N=256 and SNR=12 dB. And, though more subcarriers are used in the circumstance that the power of delayed signal is relatively great, the performance is not significantly improved.

An algorithm for cryptanalysis of certain keystream generators is proposed. The developed algorithm has the following two advantages over other reported ones: it is more powerful, and it can be implemented by a high-speed software or a simple hardware suitable for high parallel architectures. The algorithm is based on error-correction of information bits only (of the corresponding binary block code) with a novel method for construction of the parity-checks, and the employed error-correction procedure is an APP based threshold decoding. Experimental and theoretical analyses of the algorithm performance are presented, and its complexity is evaluated. The proposed algorithm is compared with recently proposed improved fast correlation attacks based on convolutional codes and turbo decoding. The underlying principles, performance and complexity are compared, and the gain obtained with the novel approach is pointed out.

At Eurocrypt'98, Okamoto and Uchiyama presented a new trap-door (one-way) function based on factoring, while Fujisaki and Okamoto, at CRYPTO'99, showed a generic conversion from just one-way encryption to chosen-cipher secure encryption in the random oracle model. This paper shows that the result of combining both schemes is well harmonized (rather than an arbitrary combination) and, in the sense of exact security, boosts the level of security more than would be expected from [6]--The security of the scheme yielded by the combination is tightly reduced from factoring. This paper also gives a rigorous description of the new scheme, because this type of encryption may suffer serious damage if poorly implemented. The proposed scheme is at least as efficient as any other chosen-cipher secure asymmetric encryption scheme such as [2],[4],[13].

Many researchers have used hypercube interconnection networks for their good properties to construct many parallel processing systems. However, as the number of processors increases, the probability of occurrences of faulty nodes also increases. Hence, for hypercube interconnection networks which have faulty nodes, several efficient dynamic routing algorithms have been proposed which allow each node to hold status information of its neighbor nodes. In this paper, we propose an improved version of the algorithm proposed by Chiu and Wu by introducing the notion of full reachability. A fully reachable node is a node that can reach all nonfaulty nodes which have Hamming distance l from the node via paths of length l. In addition, we further improve the algorithm by classifying the possibilities of detours with respect to each Hamming distance between current and target nodes. We propose an initialization procedure which makes use of an equivalent condition to perform this classification efficiently. Moreover, we conduct a simulation to measure the improvement ratio and to compare our algorithms with others. The simulation results show that the algorithms are effective when they are applied to low-dimensional hypercube interconnection networks.

Modified Edge Representation (MER) empirically proposed by one of the authors is the line integral representation for computing surface radiation integrals of diffraction. It has remarkable accuracy in surface to line integral reduction even for sources very close to the scatterer. It also overcomes false and true singularities in equivalent edge currents. This paper gives the mathematical derivation of MER by using Stokes' theorem; MER is not only asymptotic but also global approximation. It proves remarkable applicability of MER, that is, to smooth curved surface, closely located sources and arbitrary currents which are irrelevant to Maxwell equations.

A passive branched optical network unified for broadcasting and communication utilizing a set of Fabry-Perot etalons with different cavity lengths is proposed and its basic operation including thermal stability of broadcasting channel is demonstrated. It is confirmed that a high transmission frequency in common for a pair of fiber Fabry-Perot etalons is always found however environmental temperature changes.

Recently, Boneh et al. proposed an interesting algorithm for factoring integers, the so-called LFM (Lattice Factoring Method). It is based on the techniques of Coppersmith and Howgrave-Graham, namely, it cleverly employs the LLL-algorithm. The LFM is for integers of the form N = pr q, and is very effective for large r. That is, it runs in polynomial time in log N when r is on the order of log p. We note that for small r, e.g. N =pq, p2q, it is an exponential time algorithm in log N. In this paper, we propose a method for speeding up the LFM from a practical viewpoint. Also, theoretical considerations and experimental results are provided that show that the proposed algorithm offers shorter runing time than the original LFM.

In this paper, first, we propose two of the high rate methods based on Morii-Kasahara cryptosystem. Method A-I is based on Schalkwijk algorithm. Method A-II is based on the extended Schalkwijk algorithm, which is proposed in this paper. We then show that these proposed methods can yield a higher rate compared with ElGamal cryptosystem. Next, we also propose two methods for a fast encryption by dividing the message vector into several pieces. Regarding each of the divided vectors as an index, we can realize a fast transformation of the index into a limited weight vector. In Method B-I, Schalkwijk algorithm is used for the fast transformation. In Method B-II, the fast transformation is realized with the method of table-lookup. These methods can realize a faster encryption than Method A-I, Method A-II and Morii-Kasahara cryptosystem. The security of these proposed methods are based on the security of Morii-Kasahara cryptosystem.

In this paper, we investigate the performance of the orthogonal frequency division multiplexing (OFDM) system based on a configuration of pilot symbol arrangement under a time-varying fading channel and verify it by simulation. A particular channel of concern is modeled by a wide-sense stationary uncorrelated scattering (WSSUS) Rayleigh fading process and furthermore, the inter-carrier interference (ICI) caused by the fading process is assumed to be Gaussian noise. The current analysis focuses on the performance limit of the pilot symbol-assisted channel estimation, in which a minimum mean squared error (MMSE) channel estimator is employed to exploit both time- and frequency-domain correlation simultaneously. In particular, the optimum pilot symbol arrangement was investigated for the time-varying fading channel, which has been rarely addressed with any analytical approach in previous research. Although the proposed channel estimation scheme is subject to the intensive processing complexity in the receiver, it has been shown that the better BER performance can be achieved as compared with that of the differential detection scheme and the error floor can be removed.

This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: (1) Can be used in both built-in mode and off chip/module mode. (2) Can be used to test and diagnose naked arrays. (3) Fault diagnosis is simple and is "free" for some faults during test. (4) Is never subject to aliasing. (5) Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. (6) If used as built-in feature, it does not slow down the normal operation of the array. (7) Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. (8) If used as a built-in feature, the hardware overhead is very low.

This paper deals with deadlock and fairness issues that may arise when network users request resources for guaranteed service with the resource reservation protocol (RSVP). A deadlock occurs when a request can only be satisfied if the resources reserved for another request are released, but the reserved resources are never released. The fairness issue occurs when some reservation requests may be satisfied but only after a very long wait. Our approach to these issues is based on our belief that a network should provide stable throughput and fairness whatever the behavior of the user. Our methods are unique in two respects. First, during the session setup phase, a node directly connected to the requesting users terminates the users' behavior and makes reservations fairly and efficiently in place of the users. Second, our three admission control methods allocate resources for each reservation request by considering not only the current residual bandwidth but also the properties of the requesting session; e.g., its weight (the number of resources it requires) or its age (how long it has been waiting for session setup). Our methods do not maximize the throughput since they always keep a certain amount of resources unreserved for fairness. From simulation results, however, they do provide quite fair behavior, and their throughput is stable regardless of the network size and the session holding time.

In this paper we present a case study of a hierarchical statistical analysis. The method which we use here bridges the statistical information between process-level and system-level, and enables us to know the effect of the process variation on the system performance. We use two modeling techniques--intermediate model and response surface model--in order to link the statistical information between adjacent design levels. We show an experiment of the hierarchical statistical analysis applied to a Phase Locked Loop (PLL) circuit, and indicate that the hierarchical statistical analysis is practical with respect to both accuracy and simulation cost. Following three applications are also presented in order to show advantage of this linking method; these are Monte Carlo analysis, worst-case analysis, and sensitive analysis. The results of the Monte Carlo and the worst-case analysis indicate that this method is realistic statistical one. The result of the sensitive analysis enables us to evaluate the effect of process variation at the system level. Also, we can derive constraints on the process variation from a performance requirement.

Borehole radar is known as a powerful technique for monitoring of subsurface structures such as water flow. However, conventional borehole radar systems are operated in the frequency range lower than 100 MHz and the resolution is poor to measure a surface roughness and an inner structure of subsurface fractures directly. In order to monitor the water flow, these characteristics of subsurface fractures are important. We developed a polarimetric borehole radar system using dipole antennas and axial slot antennas and have found that this system can provide more information than conventional borehole radar. However, the relationship between the characteristic of subsurface fracture and the measured polarimetric radar information has not been clear. In this paper, we simulate electromagnetic wave scattering from subsurface fractures having a rough surface by Finite-Difference Time-Domain (FDTD) technique and discuss the relationship between a surface roughness of subsurface fracture and the polarimetric information. It is found that the subsurface fracture having strong cross-polarized components can be estimated to be rough surface fracture. The full polarimetric single-hole radar measurement was carried out at the Mirror Lake site, NH, USA. In this experiment, we found that subsurface fractures can be classified into some groups by an energy scattering matrix, and found that the subsurface fracture estimated to have a rough surface corresponds to that has higher water permeability.

This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera (DSC) system design show that our approach offers much faster simulation speed than register transfer level (RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.

This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.