The performance of an analog winner-take-all (WTA) circuit is affected by the corner error and the offset error. Despite the fact that the corner error can be reduced with large transconductance of the transistor, the offset error caused by device mismatch has not been completely studied. This paper presents the complete offset error analysis, and proposes low offset design guidelines and an offset cancellation scheme. The experimental results show good agreement with the theoretical analysis and the drastic improvement of the offset error.

Thinning and line extraction of binary images not only reduces data storage amount, automatically creates the adjacency and relativity between line and points but also provides applications for automatic inspection systems, pattern recognition systems and vectorization. Based on the features of construction drawings, new thinning and line extraction algorithms were proposed in this study. The experimental results showed that the proposed method has a higher reliability and produces better quality than the various existing methods.

"Dive into the Movie (DIM)" is a name of project to aim to realize a world innovative entertainment system which can provide an immersion experience into the story by giving a chance to audience to share an impression with his family or friends by watching a movie in which all audience can participate in the story as movie casts. To realize this system, several techniques to model and capture the personal characteristics instantly in face, body, gesture, hair and voice by combining computer graphics, computer vision and speech signal processing technique. Anyway, all of the modeling, casting, character synthesis, rendering and compositing processes have to be performed on real-time without any operator. In this paper, first a novel entertainment system, Future Cast System (FCS), is introduced which can create DIM movie with audience's participation by replacing the original roles' face in a pre-created CG movie with audiences' own highly realistic 3D CG faces. Then the effects of DIM movie on audience experience are evaluated subjectively. The result suggests that most of the participants are seeking for higher realism, impression and satisfaction by replacing not only face part but also body, hair and voice. The first experimental trial demonstration of FCS was performed at the Mitsui-Toshiba pavilion of the 2005 World Exposition in Aichi Japan. Then, 1,640,000 people have experienced this event during 6 months of exhibition and FCS became one of the most popular events at Expo.2005.

Human's ability to perceive elevation of a sound and distinguish whether a sound is coming from the front or rear strongly depends on the monaural spectral features of the pinnae. In order to realize an effective virtual auditory display by HRTF (head-related transfer function) customization, the pinna responses were isolated from the median HRIRs (head-related impulse responses) of 45 individual HRIRs in the CIPIC HRTF database and modeled as linear combinations of 4 or 5 basic temporal shapes (basis functions) per each elevation on the median plane by PCA (principal components analysis) in the time domain. By tuning the weight of each basis function computed for a specific height to replace the pinna response in the KEMAR HRIR at the same height with the resulting customized pinna response and listening to the filtered stimuli over headphones, 4 individuals with normal hearing sensitivity were able to create a set of HRIRs that outperformed the KEMAR HRIRs in producing vertical effects with reduced front/back ambiguity in the median plane. Since the monaural spectral features of the pinnae are almost independent of azimuthal variation of the source direction, similar vertical effects could also be generated at different azimuthal directions simply by varying the ITD (interaural time difference) according to the direction as well as the size of each individual's own head.

This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.

ACK thinning refers to the technique to discard or reduce TCP acknowledgements (ACKs) for the purpose of diverting scarce bandwidth to TCP data traffic. It has been shown that under some circumstances the technique is effective to boost the TCP throughput on wireless links, in particular the IEEE 802.11 wireless LAN (WLAN). In this letter, however, we show that ACK thinning backfires under congestion due to its cross-layer impact on the 802.11 MAC dynamics. With the ACK filtering example, we demonstrate the phenomenon and analyze the cause. Based on the analysis, we show how the IEEE 802.11 contention window size control solves the problem.

Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 44 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 44, 48, 412, ... 1616. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 µm libraries are used, the chip area and critical path of the proposed architecture are 186,411 gates and 2.79 ns, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.

A CMOS circuit is proposed which takes multiple analog input currents and extracts minimum input current at the output. It is very fast and requires no subtraction from the constant current source. It exhibits O(N) complexity and uses only 4N MOS transistors where N is the number of system inputs. This circuit consumes very little power and very small area. The substrate bias affects the threshold voltage of transistors and improves performance of the structure.

This paper proposes a new class of parallel branch-and-bound (B&B) schemes. The main idea of the scheme is to focus on the functional parallelism instead of conventional data parallelism, and to support such a heterogeneous and irregular parallelism by using a collection of autonomous agents distributed over the network. After examining several implementation issues, we describe a detail of the prototype system implemented over eight PC's connected by a network. The result of experiments conducted over the prototype system indicates that the proposed parallel processing scheme significantly improves the performance of the underlying B&B scheme by adaptively switching exploring policies adopted by each agent participating to the problem solving.

This paper discusses the least-squares linear filtering and smoothing (fixed-point and fixed-interval) problems of discrete-time signals from observations, perturbed by additive white noise, which can be randomly delayed by one sampling time. It is assumed that the Bernoulli random variables characterizing delay measurements are correlated in consecutive time instants. The marginal distribution of each of these variables, specified by the probability of a delay in the measurement, as well as their correlation function, are known. Using an innovation approach, the filtering, fixed-point and fixed-interval smoothing recursive algorithms are obtained without requiring the state-space model generating the signal; they use only the covariance functions of the signal and the noise, the delay probabilities and the correlation function of the Bernoulli variables. The algorithms are applied to a particular transmission model with stand-by sensors for the immediate replacement of a failed unit.

This paper describes a multiband vector quantization (VQ) technique based on inner product for wideband speech coding at 16 kb/s. Our approach consists of splitting the input speech into two separate bands and then applying an independent coding scheme for each band. A code excited linear prediction (CELP) coder is used in the lower band while a transform based coding strategy is applied in the higher band. The spectral components in the higher frequency band are represented by a set of modulated lapped transform (MLT) coefficients. The higher frequency band is divided into three subbands, and the MLT coefficients construct a vector for each subband. Specifically, for the VQ of these vectors, an inner product-based distance measure is proposed as a new strategy. The proposed 16 kb/s coder with the inner-product based distortion measure achieves better performance than the 48 kb/s ITU-T G.722 in subjective quality tests.

This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

Europe has initiated research activity to analyse and prepare the floor for mobile communication beyond 3G. Very recently, around the beginning of 2004, the European commission started together with the main partners in the relevant industry special projects to realize this plan. The key objective of the WINNER (Wireless World Initiative New Radio) project is to develop an innovative concept in radio access in order to address high flexibility and scalability with respect to data rates and radio environments. The future converged wireless world requires in the long-term perspective a ubiquitous radio system instead of disparate systems for different purposes (cellular, WLAN, short-range access etc.). This concept will be derived by a systematic investigation of advanced radio technologies with respect to predicted user requirements and challenging scenarios. The project will contribute to the global research, regulatory and standardisation communities and processes.

This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.

Because of the polarization dependencies of optical fiber transmission equipment, the polarization state of lightwaves inherently varies at the optical receiver input. Therefore the receiver output, especially the beat component, is very dependent on the polarization state. We derive a simple relation showing that the beat power of the lightwaves is proportional to the inner product of their Stokes vectors. Using this relation, we can systematically calculate the beat power. This calculation method can be applied to lightwaves of arbitrary polarization, such as a polarization-scrambled signal or partially polarized amplified spontaneous emission (ASE) in long-haul IM/DD systems, as well as to the signal and local oscillator lightwaves of coherent systems.

This paper presents recursive algorithms for the least mean-squared error linear filtering and fixed-interval smoothing estimators, from uncertain observations for the case of white and white plus coloured observation noises. The estimators are obtained by an innovation approach and do not use the state-space model, but only covariance information about the signal and the observation noises, as well as the probability that the signal exists in the observed values. Therefore the algorithms are applicable not only to signal processes that can be estimated by the conventional formulation using the state-space model but also to those for which a realization of the state-space model is not available. It is assumed that both the signal and the coloured noise autocovariance functions are expressed in a semi-degenerate kernel form. Since the semi-degenerate kernel is suitable for expressing autocovariance functions of non-stationary or stationary signal processes, the proposed estimators provide estimates of general signal processes.

This paper considers the least-squares linear estimation problem of signals from randomly delayed observations when the additive white noise is correlated with the signal. The delay values are treated as unknown variables, modelled by a binary white noise with values zero or one; these values indicate that the measurements arrive in time or they are delayed by one sampling time. A recursive one-stage prediction and filtering algorithm is obtained by an innovation approach and do not use the state-space model of the signal. It is assumed that both, the autocovariance functions of the signal and the crosscovariance function between the signal and the observation noise are expressed in a semi-degenerate kernel form; using this information and the delay probabilities, the estimators are recursively obtained.

We have developed a three-dimensional eye movement simulator that simulates eye movement. The simulator allows us to extract the instantaneous eye movement rotation axes from clinical data sequences. It calculates the plane formed by rotation axes and displays it on an eyeball with rotation axes. It also extracts the innervations for eye muscles. The developed simulator is mainly programmed by a CG programming language, OpenGL. First, the simulator was applied to saccadic eye movement data in order to show the so-called Listing's plane on which all hypothetical rotation axes lie. Next, it was applied to clinical data sequences of two patients with benign paroxysmal positional vertigo (BPPV). Instantaneous actual rotation axes and innervations for eye muscle extracted from data sequences have special characteristics. These results are useful for the elucidation of the mechanism of vestibular symptoms, particularly vertigo.

In this paper, design of a new analog CMOS rank-order extractor with input expandable capability is described. An rth rank-order extraction is defined that identifies the rth largest magnitude of input variables, which is useful for fuzzy controller and artificial neural networks. The architecture is realized by using maximum circuit, winner-take-all circuit, and some auxiliary circuits. The limitations and design considerations of these circuits are analyzed in this paper. An experimental chip with seven inputs is fabricated using a 0.5 µm CMOS double-poly double-metal technology. The results of measurement show the extractor with 2 µA precision, and each rank-order extraction has about 2 µs response time. The power dissipation of the experiment chip under test includes input/output pads that has 7.2 mW for 3.3 V supply voltage. The chip area of the extractor is 600 µm 700 µm.

Recently, neural networks (NNs) have been extensively applied to many signal processing problem due to their robust abilities to form complex decision regions. In particular, neural networks add flexibility to the design of equalizers for digital communication systems. Recurrent neural network (RNN) is a kind of neural network with one or more feedback loops, whereas self-organizing map (SOM) is characterized by the formation of a topographic map of the input patterns in which the spatial locations (i.e., coordinates) of the neurons in the lattice are indicative of intrinsic statistical features contained in the input patterns. In this paper, we propose a novel receiver structure by combining adaptive RNN equalizer with a SOM detector under serious ISI and nonlinear distortion in QAM system. According to the theoretical analysis and computer simulation results, the performance of the proposed scheme is shown to be quite effective in channel equalization under nonlinear distortion.