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[Keyword] LD(1872hit)

241-260hit(1872hit)

  • Exponential Neighborhood Preserving Embedding for Face Recognition

    Ruisheng RAN  Bin FANG  Xuegang WU  

     
    PAPER-Pattern Recognition

      Pubricized:
    2018/01/23
      Vol:
    E101-D No:5
      Page(s):
    1410-1420

    Neighborhood preserving embedding is a widely used manifold reduced dimensionality technique. But NPE has to encounter two problems. One problem is that it suffers from the small-sample-size (SSS) problem. Another is that the performance of NPE is seriously sensitive to the neighborhood size k. To overcome the two problems, an exponential neighborhood preserving embedding (ENPE) is proposed in this paper. The main idea of ENPE is that the matrix exponential is introduced to NPE, then the SSS problem is avoided and low sensitivity to the neighborhood size k is gotten. The experiments are conducted on ORL, Georgia Tech and AR face database. The results show that, ENPE shows advantageous performance over other unsupervised methods, such as PCA, LPP, ELPP and NPE. Another is that ENPE is much less sensitive to the neighborhood parameter k contrasted with the unsupervised manifold learning methods LPP, ELPP and NPE.

  • Room-Temperature Atomic Layer Deposition of SnO2 Using Tetramethyltin and Its Application to TFT Fabrication

    Kentaro TOKORO  Shunsuke SAITO  Kensaku KANOMATA  Masanori MIURA  Bashir AHMMAD  Shigeru KUBOTA  Fumihiko HIROSE  

     
    PAPER

      Vol:
    E101-C No:5
      Page(s):
    317-322

    We report room-temperature atomic layer deposition (ALD) of SnO2 using tetramethyltin (TMT) as a precursor and plasma-excited humidified argon as an oxidizing gas and investigate the saturation behaviors of these gases on SnO2-covered Si prisms by IR absorption spectroscopy to determine optimal precursor/oxidizer injection conditions. TMT is demonstrated to adsorb on the SnO2 surface by reacting with surface OH groups, which are regenerated by oxidizing the TMT-saturated surface by plasma-excited humidified argon. We provide a detailed discussion of the growth mechanism. We also report the RT ALD application to the RT TFT fabrication.

  • Validity of Kit-Build Method for Assessment of Learner-Build Map by Comparing with Manual Methods

    Warunya WUNNASRI  Jaruwat PAILAI  Yusuke HAYASHI  Tsukasa HIRASHIMA  

     
    PAPER-Educational Technology

      Pubricized:
    2018/01/11
      Vol:
    E101-D No:4
      Page(s):
    1141-1150

    This paper describes an investigation into the validity of an automatic assessment method of the learner-build concept map by comparing it with two well-known manual methods. We have previously proposed the Kit-Build (KB) concept map framework where a learner builds a concept map by using only a provided set of components, known as the set “kit”. In this framework, instant and automatic assessment of a learner-build concept map has been realized. We call this assessment method the “Kit-Build method” (KB method). The framework and assessment method have already been practically used in classrooms in various schools. As an investigation of the validity of this method, we have conducted an experiment as a case study to compare the assessment results of the method with the assessment results of two other manual assessment methods. In this experiment, 22 university students attended as subjects and four as raters. It was found that the scores of the KB method had a very strong correlation with the scores of the other manual methods. The results of this experiment are one of evidence to show the automatic assessment of the Kit-Build concept map can attain almost the same level of validity as well-known manual assessment methods.

  • On the Second Separating Redundancy of LDPC Codes from Finite Planes

    Haiyang LIU  Yan LI  Lianrong MA  

     
    LETTER-Coding Theory

      Vol:
    E101-A No:3
      Page(s):
    617-622

    The separating redundancy is an important concept in the analysis of the error-and-erasure decoding of a linear block code using a parity-check matrix of the code. In this letter, we derive new constructive upper bounds on the second separating redundancies of low-density parity-check (LDPC) codes constructed from projective and Euclidean planes over the field Fq with q even.

  • Implementing 128-Bit Secure MPKC Signatures

    Ming-Shing CHEN  Wen-Ding LI  Bo-Yuan PENG  Bo-Yin YANG  Chen-Mou CHENG  

     
    PAPER-Cryptography and Information Security

      Vol:
    E101-A No:3
      Page(s):
    553-569

    Multivariate Public Key Cryptosystems (MPKCs) are often touted as future-proofing against Quantum Computers. In 2009, it was shown that hardware advances do not favor just “traditional” alternatives such as ECC and RSA, but also makes MPKCs faster and keeps them competitive at 80-bit security when properly implemented. These techniques became outdated due to emergence of new instruction sets and higher requirements on security. In this paper, we review how MPKC signatures changes from 2009 including new parameters (from a newer security level at 128-bit), crypto-safe implementations, and the impact of new AVX2 and AESNI instructions. We also present new techniques on evaluating multivariate polynomials, multiplications of large finite fields by additive Fast Fourier Transforms, and constant time linear solvers.

  • Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications

    Shen-Li CHEN  Yu-Ting HUANG  Shawn CHANG  

     
    PAPER-Electromagnetic Theory

      Vol:
    E101-C No:3
      Page(s):
    143-150

    In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

  • An Efficient Content Search Method Based on Local Link Replacement in Unstructured Peer-to-Peer Networks

    Nagao OGINO  Takeshi KITAHARA  

     
    PAPER-Network

      Pubricized:
    2017/09/14
      Vol:
    E101-B No:3
      Page(s):
    740-749

    Peer-to-peer overlay networks can easily achieve a large-scale content sharing system on the Internet. Although unstructured peer-to-peer networks are suitable for finding entire partial-match content, flooding-based search is an inefficient way to obtain target content. When the shared content is semantically specified by a great number of attributes, it is difficult to derive the semantic similarity of peers beforehand. This means that content search methods relying on interest-based locality are more advantageous than those based on the semantic similarity of peers. Existing search methods that exploit interest-based locality organize multiple peer groups, in each of which peers with common interests are densely connected using short-cut links. However, content searches among multiple peer groups are still inefficient when the number of incident links at each peer is limited due to the capacity of the peer. This paper proposes a novel content search method that exploits interest-based locality. The proposed method can organize an efficient peer-to-peer network similar to the semantic small-world random graph, which can be organized by the existing methods based on the semantic similarity of peers. In the proposed method, topology transformation based on local link replacement maintains the numbers of incident links at all the peers. Simulation results confirm that the proposed method can achieve a significantly higher ratio of obtainable partial-match content than existing methods that organize peer groups.

  • Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator

    Md. Maruf HOSSAIN  Tetsuya IIZUKA  Toru NAKURA  Kunihiro ASADA  

     
    PAPER

      Vol:
    E101-A No:2
      Page(s):
    410-424

    An optimal design method for a sub-ranging Analog-to-Digital Converter (ADC) based on stochastic comparator is demonstrated by performing theoretical analysis of random comparator offset voltages. If the Cumulative Distribution Function (CDF) of the comparator offset is defined appropriately, we can calculate the PDFs of the output code and the effective resolution of a stochastic comparator. It is possible to model the analog-to-digital conversion accuracy (defined as yield) of a stochastic comparator by assuming that the correlations among the number of comparator offsets within different analog steps corresponding to the Least Significant Bit (LSB) of the output transfer function are negligible. Comparison with Monte Carlo simulation verifies that the proposed model precisely estimates the yield of the ADC when it is designed for a reasonable target yield of >0.8. By applying this model to a stochastic comparator we reveal that an additional calibration significantly enhances the resolution, i.e., it increases the Number of Bits (NOB) by ∼ 2 bits for the same target yield. Extending the model to a stochastic-comparator-based sub-ranging ADC indicates that the ADC design parameters can be tuned to find the optimal resource distribution between the deterministic coarse stage and the stochastic fine stage.

  • An Evolving Network Model for Power Grids Based on Geometrical Location Clusters

    Yun-Feng XING  Xiao CHEN  Ming-Xiang GUAN  Zhe-Ming LU  

     
    LETTER-Fundamentals of Information Systems

      Pubricized:
    2017/11/17
      Vol:
    E101-D No:2
      Page(s):
    539-542

    Considering that the traditional local-world evolving network model cannot fully reflect the characteristics of real-world power grids, this Letter proposes a new evolving model based on geographical location clusters. The proposed model takes into account the geographical locations and degree values of nodes, and the growth process is in line with the characteristics of the power grid. Compared with the characteristics of real-world power grids, the results show that the proposed model can simulate the degree distribution of China's power grids when the number of nodes is small. When the number of nodes exceeds 800, our model can simulate the USA western power grid's degree distribution. And the average distances and clustering coefficients of the proposed model are close to that of the real world power grids. All these properties confirm the validity and rationality of our model.

  • Performance Evaluation of Finite Sparse Signals for Compressed Sensing Frameworks

    Jin-Taek SEONG  

     
    LETTER-Fundamentals of Information Systems

      Pubricized:
    2017/11/06
      Vol:
    E101-D No:2
      Page(s):
    531-534

    In this paper, we consider to develop a recovery algorithm of a sparse signal for a compressed sensing (CS) framework over finite fields. A basic framework of CS for discrete signals rather than continuous signals is established from the linear measurement step to the reconstruction. With predetermined priori distribution of a sparse signal, we reconstruct it by using a message passing algorithm, and evaluate the performance obtained from simulation. We compare our simulation results with the theoretic bounds obtained from probability analysis.

  • A Compact Matched Filter Bank for an Optical ZCZ Sequence Set with Zero-Correlation Zone 2z

    Yasuaki OHIRA  Takahiro MATSUMOTO  Hideyuki TORII  Yuta IDA  Shinya MATSUFUJI  

     
    LETTER

      Vol:
    E101-A No:1
      Page(s):
    195-198

    In this paper, we propose a new structure for a compact matched filter bank (MFB) for an optical zero-correlation zone (ZCZ) sequence set with Zcz=2z. The proposed MFB can reduces operation elements such as 2-input adders and delay elements. The number of 2-input adders decrease from O(N2) to O(N log2 N), delay elements decrease from O(N2) to O(N). In addition, the proposed MFBs for the sequence of length 32, 64, 128 and 256 with Zcz=2,4 and 8 are implemented on a field programmable gate array (FPGA). As a result, the numbers of logic elements (LEs) of the proposed MFBs for the sequences with Zcz=2 of length 32, 64, 128 and 256 are suppressed to about 76.2%, 84.2%, 89.7% and 93.4% compared to that of the conventional MFBs, respectively.

  • Efficient Three-Way Split Formulas for Binary Polynomial Multiplication and Toeplitz Matrix Vector Product

    Sun-Mi PARK  Ku-Young CHANG  Dowon HONG  Changho SEO  

     
    PAPER-Algorithms and Data Structures

      Vol:
    E101-A No:1
      Page(s):
    239-248

    In this paper, we present a new three-way split formula for binary polynomial multiplication (PM) with five recursive multiplications. The scheme is based on a recently proposed multievaluation and interpolation approach using field extension. The proposed PM formula achieves the smallest space complexity. Moreover, it has about 40% reduced time complexity compared to best known results. In addition, using developed techniques for PM formulas, we propose a three-way split formula for Toeplitz matrix vector product with five recursive products which has a considerably improved complexity compared to previous known one.

  • Shoulder-Surfing Resistant Authentication Using Pass Pattern of Pattern Lock

    So HIGASHIKAWA  Tomoaki KOSUGI  Shogo KITAJIMA  Masahiro MAMBO  

     
    PAPER

      Pubricized:
    2017/10/16
      Vol:
    E101-D No:1
      Page(s):
    45-52

    We study an authentication method using secret figures of Pattern Lock, called pass patterns. In recent years, it is important to prevent the leakage of personal and company information on mobile devices. Android devices adopt a login authentication called Pattern Lock, which achieves both high resistance to Brute Force Attack and usability by virtue of pass pattern. However, Pattern Lock has a problem that pass patterns directly input to the terminal can be easily remembered by shoulder-surfing attack. In this paper, we propose a shoulder-surfing resistant authentication using pass pattern of Pattern Lock, which adopts a challenge & response authentication and also uses users' short-term memory. We implement the proposed method as an Android application and measure success rate, authentication time and the resistance against shoulder surfing. We also evaluate security and usability in comparison with related work.

  • Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology

    Toru TANZAWA  

     
    PAPER-Electronic Circuits

      Vol:
    E101-C No:1
      Page(s):
    78-81

    This paper discusses design challenges and possible solutions for 3D NAND. A 3D NAND array inherently has a larger parasitic capacitance and thereby critical area in terms of product yield. To mitigate such issues associated with 3D NAND technology, array control and divided array architecture for improving reliability and yield and for reducing area overhead, program time, energy per bit and array noise are proposed.

  • An Efficient Acoustic Distance Rendering Algorithm for Proximity Control in Virtual Reality Systems

    Yonghyun BAEK  Tegyu LEE  Young-cheol PARK  

     
    LETTER-Digital Signal Processing

      Vol:
    E100-A No:12
      Page(s):
    3054-3060

    In this letter, we propose an acoustic distance rendering (ADR) algorithm that can efficiently create the proximity effect in virtual reality (VR) systems. By observing the variation of acoustic cues caused by the movement of the sound source in the near field, we develop a model that can closely approximates the near-field transfer function (NFTF). The developed model is used to efficiently compensate for the near-field effect on the head related transfer function (HRTF). The proposed algorithm is implemented and tested in the form of an audio plugin for a VR platform and the test results confirm the efficiency of the proposed algorithm.

  • Provably Secure Gateway Threshold Password-Based Authenticated Key Exchange Secure against Undetectable On-Line Dictionary Attack

    Yukou KOBAYASHI  Naoto YANAI  Kazuki YONEYAMA  Takashi NISHIDE  Goichiro HANAOKA  Kwangjo KIM  Eiji OKAMOTO  

     
    PAPER-Cryptography and Information Security

      Vol:
    E100-A No:12
      Page(s):
    2991-3006

    By using Password-based Authenticated Key Exchange (PAKE), a server can authenticate a user who has only the same password shared with the server in advance and establish a session key with the user simultaneously. However, in the real applications, we may have a situation where a user needs to share a session key with server A, but the authentication needs to be done by a different server B that shares the password with the user. Further, to achieve higher security on the server side, it may be required to make PAKE tolerant of a server breach by having multiple authentication servers. To deal with such a situation, Abdalla et al. proposed a variant of PAKE called Gateway Threshold PAKE (GTPAKE) where a gateway corresponds to the aforementioned server A being an on-line service provider and also a potential adversary that may try to guess the passwords. However, the schemes of Abdalla et al. turned out to be vulnerable to Undetectable On-line Dictionary Attack (UDonDA). In this paper, we propose the first GTPAKE provably secure against UDonDA, and in the security analysis, we prove that our GTPAKE is secure even if an adversary breaks into parts of multiple authentication servers.

  • Improved Sphere Bound on the MLD Performance of Binary Linear Block Codes via Voronoi Region

    Jia LIU  Meilin HE  Jun CHENG  

     
    PAPER-Coding Theory and Techniques

      Vol:
    E100-A No:12
      Page(s):
    2572-2577

    In this paper, the Voronoi region of the transmitted codeword is employed to improve the sphere bound on the maximum-likelihood decoding (MLD) performance of binary linear block codes over additive white Gaussian noise (AWGN) channels. We obtain the improved sphere bounds both on the frame-error probability and the bit-error probability. With the framework of the sphere bound proposed by Kasami et al., we derive the conditional decoding error probability on the spheres by defining a subset of the Voronoi region of the transmitted codeword, since the Voronoi regions of a binary linear block code govern the decoding error probability analysis over AWGN channels. The proposed bound improves the sphere bound by Kasami et al. and the sphere bound by Herzberg and Poltyrev. The computational complexity of the proposed bound is similar to that of the sphere bound by Kasami et al.

  • Adaptive Thresholding for Signal De-Noising for Power-Line Communications

    Yu Min HWANG  Gyeong Hyeon CHA  Jong Kwan SEO  Jae-Jo LEE  Jin Young KIM  

     
    LETTER-Digital Signal Processing

      Vol:
    E100-A No:12
      Page(s):
    3041-3044

    This paper proposes a novel wavelet de-noising scheme regarding the existing burst noises that consist of background and impulsive noises in power-line communications. The proposed de-noising scheme employs multi-level threshold functions to efficiently and adaptively reduce the given burst noises. The experiment results show that the proposed de-noising scheme significantly outperformed the conventional schemes.

  • A Region-Based Through-Silicon via Repair Method for Clustered Faults

    Tianming NI  Huaguo LIANG  Mu NIE  Xiumin XU  Aibin YAN  Zhengfeng HUANG  

     
    PAPER-Integrated Electronics

      Vol:
    E100-C No:12
      Page(s):
    1108-1117

    Three-dimensional integrated circuits (3D ICs) that employ through-silicon vias (TSVs) integrating multiple dies vertically have opened up the potential of highly improved circuit designs. However, various types of TSV defects may occur during the assembly process, especially the clustered TSV faults because of the winding level of thinned wafer, the surface roughness and cleanness of silicon dies,inducing TSV yield reduction greatly. To tackle this fault clustering problem, router-based and ring-based TSV redundancy architectures were previously proposed. However, these schemes either require too much area overhead or have limited reparability to tolerant clustered TSV faults. Furthermore, the repairing lengths of these schemes are too long to be ignored, leading to additional delay overhead, which may cause timing violation. In this paper, we propose a region-based TSV redundancy design to achieve relatively high reparability as well as low additional delay overhead. Simulation results show that for a given number of TSVs (8*8) and TSV failure rate (1%), our design achieves 11.27% and 20.79% reduction of delay overhead as compared with router-based design and ring-based scheme, respectively. In addition, the reparability of our proposed scheme is much better than ring-based design by 30.84%, while it is close to that of the router-based scheme. More importantly, the overall TSV yield of our design achieves 99.88%, which is slightly higher than that of both router-based method (99.53%) and ring-based design (99.00%).

  • Spatially “Mt. Fuji” Coupled LDPC Codes

    Yuta NAKAHARA  Shota SAITO  Toshiyasu MATSUSHIMA  

     
    PAPER-Coding Theory and Techniques

      Vol:
    E100-A No:12
      Page(s):
    2594-2606

    A new type of spatially coupled low density parity check (SCLDPC) code is proposed. This code has two benefits. (1) This code requires less number of iterations to correct the erasures occurring through the binary erasure channel in the waterfall region than that of the usual SCLDPC code. (2) This code has lower error floor than that of the usual SCLDPC code. Proposed code is constructed as a coupled chain of the underlying LDPC codes whose code lengths exponentially increase as the position where the codes exist is close to the middle of the chain. We call our code spatially “Mt. Fuji” coupled LDPC (SFCLDPC) code because the shape of the graph representing the code lengths of underlying LDPC codes at each position looks like Mt. Fuji. By this structure, when the proposed SFCLDPC code and the original SCLDPC code are constructed with the same code rate and the same code length, L (the number of the underlying LDPC codes) of the proposed SFCLDPC code becomes smaller and M (the code lengths of the underlying LDPC codes) of the proposed SFCLDPC code becomes larger than those of the SCLDPC code. These properties of L and M enables the above reduction of the number of iterations and the bit error rate in the error floor region, which are confirmed by the density evolution and computer simulations.

241-260hit(1872hit)