Quaternionic neural networks are extensions of neural networks using quaternion algebra. 3-D and 4-D quaternionic MLPs have been studied. 3-D quaternionic neural networks are useful for handling 3-D objects, such as Euclidean transformation. As for Hopfield neural networks, only 4-D quaternionic Hopfield neural networks (QHNNs) have been studied. In this work, we propose the 3-D QHNNs. Moreover, we define the energy, and prove that it converges.

This paper proposes 0-1-A-Ā LUT, a new programmable logic using atom switches, and a delay-optimal mapping algorithm for it. Atom switch is a non-volatile memory device of very small geometry which is fabricated between metal layers of a VLSI, and it can be used as a switch device of very small on-resistance and parasitic capacitance. While considerable area reduction of Look Up Tables (LUTs) used in conventional Field Programmable Gate Arrays (FPGAs) has been achieved by simply replacing each SRAM element with a memory element using a pair of atom switches, our 0-1-A-Ā LUT achieves further area and delay reduction. Unlike the conventional atom-switch-based LUT in which all k input signals are fed to a MUX, one of input signals is fed to the switch array, resulting area reduction due to the reduced number of inputs of the MUX from 2k to 2k-1, as well as delay reduction due to reduced fanout load of the input buffers. Since the fanout of this input buffers depends on the mapped logic function, this paper also proposes technology mapping algorithms to select logic function of fewer number of fanouts of input buffers to achieve further delay reduction. From our experiments, the circuit delay using our k-LUT is 0.94% smaller in the best case compared with using the conventional atom-switch-based k-LUT.

Multiple image group cosegmentation (MGC) aims at segmenting common object from multiple group of images, which is a new cosegmentation research topic. The existing MGC methods formulate MGC as label assignment problem (Markov Random Field framework), which is observed to be sensitive to parameter setting. Meanwhile, it is also observed that large object variations and complicated backgrounds dramatically decrease the existing MGC performance. To this end, we propose a new object proposal based MGC model, with the aim of avoiding tedious parameter setting, and improving MGC performance. Our main idea is to formulate MGC as new region proposal selection task. A new energy function in term of proposal is proposed. Two aspects such as the foreground consistency within each single image group, and the group consistency among image groups are considered. The energy minimization method is designed in EM framework. Two steps such as the loop belief propagation and foreground propagation are iteratively implemented for the minimization. We verify our method on ICoseg dataset. Six existing cosegmentation methods are used for the comparison. The experimental results demonstrate that the proposed method can not only improve MGC performance in terms of larger IOU values, but is also robust to the parameter setting.

In this paper, we present sub-1-V CMOS-based electrophoresis method for small-form-factor biomolecule manipulation that is contained in a microchip. This is the first time this type of device has been presented in the literature. By combining CMOS technology with electroless gold plating, the electrode pitch can be reduced and the required input voltage can be decreased to less than 1 V. We fabricated the CMOS electrophoresis chip in a cost-competitive 0.6 µm standard CMOS process. A sample/hold circuit in each cell is used to generate a constant output from an analog input. After forming gold electrodes using an electroless gold plating technique, we were able to manipulate red food coloring with a 0-0.7 V input voltage range. The results shows that the proposed CMOS chip is effective for electrophoresis-based manipulation.

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (Vh) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (Vt1) and the Vh values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (It2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.

The purpose of DNA sequencing is to determine the order of nucleotides within a DNA molecule of target. The target DNA molecules are fragmented into short reads, which are short fixed-length subsequences composed of ‘A’, ‘C’, ‘G’ ‘T’, by next generation sequencing (NGS) machine. To reconstruct the target DNA from the short reads using a reference genome, which is a representative example of a species that was constructed in advance, it is necessary to determine their locations in the target DNA from where they have been extracted by aligning them onto the reference genome. This process is called short read mapping, and it is important to improve the performance of the short read mapping to realize fast DNA sequencing. We propose three types of FPGA acceleration methods based on hash table; (1) sorting and parallel comparison, (2) matching that allows one mutation to reduce the number of the candidates, (3) optimized hash function using variable masks. The first one reduces the number of accesses to off-chip memory to avoid the bottleneck by access latency. The second one enables to reduce the number of the candidates without degrading mapping sensitivity by allowing one mutation in the comparison. The last one reduces hash collisions using a table that was calculated from the reference genome in advance. We implemented the three methods on Xilinx Virtex-7 and evaluated them to show their effectiveness of them. In our experiments, our system achieves 20 fold of processing speed compared with BWA, which is one of the most popular mapping tools. Furthermore, we shows that the our system outperforms one of the fastest FPGA short read mapping systems.

In this letter, we propose a round robin-based wear leveling (RRWL) for flash memory systems. RRWL uses a block erase table (BET), which is composed of a bit array and saves the erasure histories of blocks. BET can use one-to-one mode to increase the performance of wear leveling or one-to-many mode to reduce memory consumption. However, one-to-many mode decreases the accuracy of cold block information, which results in the lifetime degradation of flash memory. To solve this problem, RRWL consistently uses one-to-one mode based on round robin method to increase the accuracy of cold block identification, with reduced memory size of BET, like in one-to-many mode. Experiments show that RRWL increases the lifetime of flash memory by up to 47% and 14%, compared with BET and HaWL, respectively.

The performance of devices based on two dimensional (2D) materials is significantly affected upon prolonged exposure to atmosphere. We analyzed time based environmental degradation of electrical properties of HfS2 field effect transistors. Atmospheric entities like oxygen and moisture adversely affect the device surface and reduction in drain current is observed over period of 48 hours. Two corrective measures, namely, PMMA passivation and vacuum annealing, have been studied to address the diminution of current by contaminants. PMMA passivation prevents the device from environment and reduces the effect of Coulomb scattering. Improvement in current characteristics signifies the importance of dielectric passivation for 2D materials. On the other hand, vacuum annealing is useful in removing contaminants from the affected surface. In order to figure out optimum process conditions, properties have been studied at various annealing temperatures. The improvement in drain current level was observed upon vacuum annealing within optimum range of annealing temperature.

In this paper, the effect of a nitrogen-doped (N-doped) LaB6 interfacial layer (IL) on p-type pentacene-based OFET was investigated. The pentacene-based OFET with top-contact/back-gate geometry was fabricated. A 2-nm-thick N-doped LaB6 interfacial layer deposited on an 8-nm-thick SiO2 gate insulator. A 10-nm-thick pentacene film was deposited by thermal evaporation at 100°C followed by Au contact and Al back gate electrodes formation. The fabricated OFET showed normally- off characteristics and a steep subthreshold swing (SS) of 84 mV/dec. from ID-VG and ID-VD characteristics. Furthermore, the aging characteristics of 6 months after the fabrication were investigated and it was found that VTH and SS were stable when the N-doped LaB6 IL was introduced at the interface between SiO2 gate insulator and pentacene.

When synthesizing speech from Japanese text, correct assignment of accent nuclei for input text with arbitrary contents is indispensable in obtaining naturally-sounding synthetic speech. A phenomenon called accent sandhi occurs in utterances of Japanese; when a word is uttered in a sentence, its accent nucleus may change depending on the contexts of preceding/succeeding words. This paper describes a statistical method for automatically predicting the accent nucleus changes due to accent sandhi. First, as the basis of the research, a database of Japanese text was constructed with labels of accent phrase boundaries and accent nucleus positions when uttered in sentences. A single native speaker of Tokyo dialect Japanese annotated all the labels for 6,344 Japanese sentences. Then, using this database, a conditional-random-field-based method was developed using this database to predict accent phrase boundaries and accent nuclei. The proposed method predicted accent nucleus positions for accent phrases with 94.66% accuracy, clearly surpassing the 87.48% accuracy obtained using our rule-based method. A listening experiment was also conducted on synthetic speech obtained using the proposed method and that obtained using the rule-based method. The results show that our method significantly improved the naturalness of synthetic speech.

As seen in stream data processing, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M,N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers (MUXs). However, the number of required MUXs increases too much as the input/output byte widths increase. It is known that partitioning a MUX network leads to reducing the number of MUXs. In this paper, we firstly pick up a multi-layered MUX network, which is generated by repeatedly partitioning a MUX network into a collection of single-layered MUX networks. We show that the multi-layered MUX network is equivalent to the barrel shifter from which redundant MUXs and wires are removed, and we prove that the number of required MUXs becomes the smallest among MUX-network-partitioning based field-data extractors. Next, we propose a rotator-based MUX network for a field-data extractor, which is based on reading out a particular data in an input register to a rotator. The byte width of the rotator is the same as its output register and hence we no longer require any extra wires nor MUXs. By rotating the input data appropriately, we can finally have a right-ordered data into an output register. Experimental results show that a multi-layered MUX network reduces the number of required gates to construct a field-data extractor by up to 97.0% compared with the one using a naive approach and its delay becomes 1.8ns-2.3ns. A rotator-based MUX network with a control circuit also reduces the number of required gates to construct a field-data extractor by up to 97.3% compared with the one using a naive approach and its delay becomes 2.1ns-2.9ns.

Due to the rapid growth of applications that are based on Internet of Things (IoT) and real-time communications, mobile traffic growth is increasing exponentially. In highly populated areas, sudden concentration of numerous mobile user traffic can cause radio resource shortage, where traffic offloading is essential in preventing overload problems. Vertical handover (VHO) technology which supports seamless connectivity across heterogeneous wireless networks is a core technology of traffic offloading. In VHO, minimizing service interruption is a key design factor, since service interruption deteriorates service performance and degrades user experience (UX). Although 3GPP standard VHO procedures are designed to prevent service interruption, severe quality of service (QoS) degradation and severe interruption can occur in real network environments due to unintended disconnections with one's base station (BS) or access point (AP). In this article, the average minimum handover interruption time (HIT) (i.e., the guaranteed HIT influence) between LTE and Wi-Fi VHO is analyzed and measured based on 3GPP VHO access and decision procedures. In addition, the key parameters and procedures which affect HIT performance are analyzed, and a reference probability density function (PDF) for HIT prediction is derived from Kolmogorov-Smirnov test techniques.

This paper presents a design optimization method for a Gm-C active filter via geometric programming (GP). We first describe a GP-compatible model of a cascaded Gm-C filter that forms a biquadratic output transfer function. The bias, gain, bandwidth, and signal-to-noise ratio (SNR) of the Gm-C filter are described in a GP-compatible way. To further enhance the accuracy of the model, two modeling techniques are introduced. The first, a two-step selection method, chooses whether a saturation or subthreshold model should be used for each transistor in the filter to enhance the modeling accuracy. The second, a bisection method, is applied to include non-posynomial inequalities in the filter modeling. The presented filter model is optimized via a GP solver along with proposed modeling techniques. The numerical experiments over wide ranges of design specifications show good agreement between model and simulation results, with the average error for gain, bandwidth, and SNR being less than 9.9%, 4.4%, and 14.6%, respectively.

Compressed sensing (CS)-based wideband spectrum sensing has been a hot topic because it can cut high signal acquisition costs. However, using CS-based approaches, the spectral recovery requires large computational complexity. This letter proposes a wideband spectrum sensing algorithm based on multirate coprime sampling. It can detect the entire wideband directly from sub-Nyquist samples without spectral recovery, thus it brings a significant reduction of computational complexity. Compared with the excellent spectral recovery algorithm, i.e., orthogonal matching pursuit, our algorithm can maintain good sensing performance with computational complexity being several orders of magnitude lower.

The major task in compact modeling for high power devices is to predict the switching waveform accurately because it determines the energy loss of circuits. Device capacitance mainly determines the switching characteristics, which makes accurate capacitance modeling inevitable. This paper presents a newly developed compact model HiSIM-GaN [Hiroshima University STARC IGFET Model for Gallium-Nitride-based High Electron Mobility Transistors (GaN-HEMTs)], where the focus is given on the accurate modeling of the field-plate (FP), which is introduced to delocalize the electric-field peak that occurs at the electrode edge. We demonstrate that the proposed model reproduces capacitance measurements of a GaN-HEMT accurately without fitting parameters. Furthermore, the influence of the field plate on the studied circuit performance is analyzed.

It is well known that spatially coupled (SC) codes with erasure-BP decoding have powerful error correcting capability over memoryless erasure channels. However, the decoding performance of SC-codes significantly degrades when they are used over burst erasure channels. In this paper, we propose band splitting permutations (BSP) suitable for (l,r,L) SC-codes. The BSP splits a diagonal band in a base matrix into multiple bands in order to enhance the span of the stopping sets in the base matrix. As theoretical performance guarantees, lower and upper bounds on the maximal burst correctable length of the permuted (l,r,L) SC-codes are presented. Those bounds indicate that the maximal correctable burst ratio of the permuted SC-codes is given by λmax≃1/k where k=r/l. This implies the asymptotic optimality of the permuted SC-codes in terms of burst erasure correction.

Based on the codewords of the [q,2,q-1] extended Reed-Solomon (RS) code over the finite field Fq, we can construct a regular binary γq×q2 matrix H(γ,q), where q is a power of 2 and γ≤q. The matrix H(γ,q) defines a regular low-density parity-check (LDPC) code C(γ,q), called a full-length RS-LDPC code. Using some analytical methods, we completely determine the values of s(H(4,q)), s(H(5,q)), and d(C(5,q)) in this letter, where s(H(γ,q)) and d(C(γ,q)) are the stopping distance of H(γ,q) and the minimum distance of C(γ,q), respectively.

The mixer is a crucial circuit block in a WiMax system receiver. The performance of a mixer depends on three specifications: conversion gain, linearity and noise figure. Many mixers have been recently proposed for UWB and wideband systems; however, they either cannot achieve the high conversion gain required for a WiMAX system or they are prone to high power consumption. In this paper, a folded mixer with a high conversion gain is designed for a 2-11GHz WiMAX system and it can achieve a 20MHz IF output signal. From the simulation results, the proposed folded mixer achieves a conversion gain of 18.9 to 21.5dB for the full bandwidth. With a 0.2 to 4.4dBm IIP3, the NF is 13.5 to 17.6dB. The folded mixer is designed using TSMC 0.18µm CMOS technology. The core power consumption of the mixer is 11.8mW.

We integrate a pressure sensing capacitor and a low operation voltage OFET to develop a pressure sensor. The OFET was used as a readout device and an external pressure was loaded on the sensing capacitor. The OFET operates at less than 5 V and the change in the drain current in response to the pressure load (100 kPa) is two orders of magnitude.