Considering that the traditional local-world evolving network model cannot fully reflect the characteristics of real-world power grids, this Letter proposes a new evolving model based on geographical location clusters. The proposed model takes into account the geographical locations and degree values of nodes, and the growth process is in line with the characteristics of the power grid. Compared with the characteristics of real-world power grids, the results show that the proposed model can simulate the degree distribution of China's power grids when the number of nodes is small. When the number of nodes exceeds 800, our model can simulate the USA western power grid's degree distribution. And the average distances and clustering coefficients of the proposed model are close to that of the real world power grids. All these properties confirm the validity and rationality of our model.

There have been several recent reports that botnet communication between bot-infected computers and Command and Control servers (C&C servers) using the Domain Name System (DNS) protocol has been used by many cyber attackers. In particular, botnet communication based on the DNS TXT record type has been observed in several kinds of botnet attack. Unfortunately, the DNS TXT record type has many forms of legitimate usage, such as hostname description. In this paper, in order to detect and block out botnet communication based on the DNS TXT record type, we first differentiate between legitimate and suspicious usages of the DNS TXT record type and then analyze real DNS TXT query data obtained from our campus network. We divide DNS queries sent out from an organization into three types — via-resolver, and indirect and direct outbound queries — and analyze the DNS TXT query data separately. We use a 99-day dataset for via-resolver DNS TXT queries and an 87-day dataset for indirect and direct outbound DNS TXT queries. The results of our analysis show that about 30%, 8% and 19% of DNS TXT queries in via-resolver, indirect and direct outbound queries, respectively, could be identified as suspicious DNS traffic. Based on our analysis, we also consider a comprehensive botnet detection system and have designed a prototype system.

This paper aims to improve the ability of low voltage ride through (LVRT) of doubly-fed induction generation (DFIG) under the asymmetric grid fault. The traditional rotor of the Crowbar device requires a large reactive support during the period of protection, which causes large fluctuations to the reactive power of the output grid while cut in and off for Crowbar. This case would influence the quality and efficiency of entire power system. In order to solve the fluctuation of reactive power and the stability of the wind power system, this paper proposes the coordinated control of the fuzzy-neural D-STATCOM and the rotor of the Crowbar. The simulation results show that the system has the performance of the rotor current with faster decay and faster dynamic response, high steady-state characteristic during the grid fault, which improve the ability of LVRT of DFIG.

We developed a system called DELTA that supports the students' use of backward chaining (BC) to prove the congruence of two triangles. DELTA is designed as an interactive learning environment and supports the use of BC by providing hints and a function to automatically check the proofs inputted by the students. DELTA also has coloring, marking, and highlighting functions to support students' attempts to prove the congruence of two triangles. We evaluated the efficacy of DELTA with 36 students in the second grade of a junior high school in Japan. We found that (1) the mean number of problems, which the experimental group (EG) completely solved, was statistically higher than that of the control group on the post-test; (2) the EG effectively used the BC strategy to solve problems; and (3) the students' attempt to use both the forward chaining strategy and the BC strategy led to solving the problems completely.

This study is aimed at clarifying the mechanism of wear process for Ag plating. The samples of different hardness Ag plating on copper alloys were prepared as coupon and embossment specimens, which simulated terminal contacts. During the sliding test, the contact resistance and the friction coefficient versus sliding distance are measured. The surface observation and surface roughness of the Ag films after wear tests were investigated. As results, the hard Ag plating film (120 Hv) exhibited higher contact resistance comparing to the soft Ag plating film (80 Hv). The soft Ag film delivered wider wear trace on coupon specimens compared to the hard one. Moreover, the observation of tribofilms formed on the Ag films after wear tests suggested that a mixed-type of adhesive and abrasive wears occurred for both of soft and hard Ag films. Furthermore, the fretting corrosion resistance of Ag plating samples with different hardness was also investigated. As results, the wear resistance of hard Ag film was stronger than that of soft Ag film.

Process and temperature variations have become a serious concern for ultra-low voltage (ULV) technology. The clock generator is the essential component for the ULV very-large-scale integration (VLSI). MOSFETs that are operated in the sub-threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. In this paper, process and temperature variations on the clock generators have been studied. This paper presents an ultra-low voltage 2.4GHz CMOS voltage controlled oscillator with temperature and process compensation. A new all-digital auto compensated mechanism to reduce process and temperature variation without any laser trimming is proposed. With the compensated circuit, the VCO frequency-drift is 16.6 times the improvements of the uncompensated one as temperature changes. Furthermore, it also provides low jitter performance.

Verification of logic designs has been a long-standing bottleneck in the process of hardware design, where its automation and improvement of efficiency has demanding needs. Mainly simulation-based verification has been used for this purpose, and recently, coverage-driven verification has been widely used, of which target is improvement of some metric called coverage. Our target is the metric called toggle coverage. To find input patterns which cause some toggles on each signal, a SAT solver could be used, but this is computationally costly. In this paper, we study the effect of combination of random simulation and usage of a SAT solver. In particular, we use a SAT solver which can find multiple “diverse” solutions. With this solver, we can avoid generating similar patterns, which are unlikely to improve coverage. The experimental results show that, a small number of calls of a SAT solver can improve entire toggle coverage effectively, compared with simple random simulation.

Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.

In this paper, a Boolean algebra approach is proposed to encode various acceptability semantics for abstract argumentation frameworks, where each semantics can be equivalently encoded into several Boolean constraint models based on Boolean matrices and a family of Boolean operations between them. Then, we show that these models can be easily translated into logic programs, and can be solved by a constraint solver over Boolean variables. In addition, we propose some querying strategies to accelerate the calculation of the grounded, stable and complete extensions. Finally, we describe an experimental study on the performance of our encodings according to different semantics and querying strategies.

A Reed-Solomon (RS) decoder is designed based on the pipelined recursive Euclidean algorithm in the key equation solution. While the Euclidean algorithm uses less Galois multipliers than the modified Euclidean (ME) and reformulated inversionless Berlekamp-Massey (RiBM) algorithms, division between two elements in Galois field is required. By implementing the division with a multi-cycle Galois inverter and a serial Galois multiplier, the proposed key equation solver architecture achieves lower complexity than the conventional ME and RiBM based architectures. The proposed RS (255,239) decoder reduces the hardware complexity by 25.9% with 6.5% increase in decoding latency.

The classification of warheads and decoys is a core technology in the defense of the ballistic missile. Usually, a high range resolution is favorable for the development of the classification algorithm, which requires a high sampling rate in fast time, and thus leads to a heavy computation burden for data processing. In this paper, a novel method based on compressed sensing (CS) is presented to improve the range resolution of the target with low computational complexity. First, a tool for electromagnetic calculation, such as CST Microwave Studio, is used to simulate the frequency response of the electromagnetic scattering of the target. Second, the range-resolved signal of the target is acquired by further processing. Third, a greedy algorithm is applied to this signal. By the iterative search of the maximum value from the signal rather than the calculation of the inner product for raw echo, the scattering coefficients of the target can be reconstructed efficiently. A series of experimental results demonstrates the effectiveness of our method.

Most Android applications are written in JAVA and run on a Dalvik virtual machine. For smartphone vendors and users who wish to know the performance of an application on a particular smartphone but cannot obtain the source code, we propose a new technique, Dalvik Profiler for Applications (DPA), to profile an Android application on a Dalvik virtual machine without the support of source code. Within a Dalvik virtual machine, we determine the entry and exit locations of a method, log its execution time, and analyze the log to determine the performance of the application. Our experimental results show an error ratio of less than 5% from the baseline tool Traceview which instruments source code. The results also show some interesting behaviors of applications and smartphones: the performance of some smartphones with higher hardware specifications is 1.5 times less than the phones with lower specifications. DPA is now publicly available as an open source tool.

Web Service Business Process Execution Language (BPEL) has become the de facto standard for developing instant service-oriented workflow applications in open environment. The correctness and reliability of BPEL processes have gained increasing concerns. However, the unique features (e.g., dead path elimination (DPE) semantics, parallelism, etc.) of BPEL language have raised enormous problems to it, especially in path feasibility analysis of BPEL processes. Path feasibility analysis of BPEL processes is the basis of BPEL testing, for it relates to the test case generation. Since BPEL processes support both parallelism and DPE semantics, existing techniques can't be directly applied to its path feasibility analysis. To address this problem, we present a novel technique to analyze the path feasibility for BPEL processes. First, to tackle unique features mentioned above, we transform a BPEL process into an intermediary model — BPEL control flow graph, which is proposed to abstract the execution flow of BPEL processes. Second, based on this abstraction, we symbolically encode every path of BPEL processes as some Satisfiability formulas. Finally, we solve these formulas with the help of Satisfiability Modulo Theory (SMT) solvers and the feasible paths of BPEL processes are obtained. We illustrate the applicability and feasibility of our technique through a case study.

The Process Virtual Machine (VM) is typical software that runs applications inside operating systems. Its purpose is to provide a platform-independent programming environment that abstracts away details of the underlying hardware, operating system and allows bytecodes (portable code) to be executed in the same way on any other platforms. The Process VMs are implemented using an interpreter to interpret bytecode instead of direct execution of host machine codes. Thus, the bytecode execution is slower than those of the compiled programming language execution. Several techniques including our previous paper, the “Fetch/Decode Hardware Extension”, have been proposed to speed up the interpretation of Process VMs. In this paper, we propose an additional methodology, the “Hardware Extension with Hybrid Execution” to further enhance the performance of Process VMs interpretation and focus on Register-based model. This new technique provides an additional decoder which can classify bytecodes into either simple or complex instructions. With “Hybrid Execution”, the simple instruction will be directly executed on hardware of native processor. The complex instruction will be emulated by the “extra optimized bytecode software handler” of native processor. In order to eliminate the overheads of retrieving and storing operand on memory, we utilize the physical registers instead of (low address) virtual registers. Moreover, the combination of 3 techniques: Delay scheduling, Mode predictor HW and Branch/goto controller can eliminate all of the switching mode overheads between native mode and bytecode mode. The experimental results show the improvements of execution speed on the Arithmetic instructions, loop & conditional instructions and method invocation & return instructions can be achieved up to 16.9x, 16.1x and 3.1x respectively. The approximate size of the proposed hardware extension is 0.04mm2 (or equivalent to 14.81k gates) and consumes an additional power of only 0.24mW. The stated results are obtained from logic synthesis using the TSMC 90nm technology @ 200MHz.

In this paper, the repeatable hybrid parallel implementation of inverse matrix computation using SMW formula is proposed. The authors' had previously proposed a hybrid parallel algorithm for inverse matrix computation. It is reasonably fast for a one time computation of an inverse matrix, but it is hard to apply this algorithm repeatedly for consecutive computations since the relocation of the large matrix is required at the beginning of each iterations. In order to eliminate the relocation of the large input matrix which is the output of the inverse matrix computation from the previous time step, the computation algorithm has been redesigned so that the required portion of the input matrix becomes the same as the output portion of the previously computed matrix in each node. This makes it possible to repeatedly and efficiently apply the SMW formula to compute inverse matrix in a time-series simulation.

We investigated a control of the crystalline orientation of soluble organic semiconductor single crystals using liquid crystal solvents aligned by the electric field to improve the performance of organic thin-film transistors. We clarified that the semiconductor single crystal grows to the direction parallel to the liquid crystal alignment oriented by the lateral electric field.

The number of states is a very important matter for model checking approach in Petri net's analysis. We first gave a formal definition of state number calculation problem: For a Petri net with an initial state (marking), how many states does it have? Next we showed the problem cannot be solved in polynomial time for a popular subclass of Petri nets, known as free choice workflow nets, if P≠NP. Then we proposed a polynomial time algorithm to solve the problem by utilizing a representational bias called as process tree. We also showed effectiveness of the algorithm through an application example.

The combination of a halogen-free solvent 1,2,4-trimethylbenzene and unmodified fullerene potentially provides a way to develop environmentally-friendly and cost-effective solution-processed organic photocells. In this paper, the thermal annealing effect on the optical absorption spectra in poly(3-hexylthiophene):unmodified-C$_{60}$ composites with various compositions is reported. It is found that the onset temperature of the absorption spectrum change is higher in the composites with higher fullerene content. It is speculated that strong interaction between the polymer main chain and C$_{60}$ tends to suppress the reorientation of polymer main chains in a composite with high C$_{60}$ content.

We have investigated both the film thickness and surface potential of organic semiconductors deposited on two kinds of electrodes by the simultaneous observation with the dynamic force microscopy (DFM)/Kelvin-probe force microscope (KFM). To clarify the interfacial properties of organic semiconductor, we fabricated samples that imitated the organic light emitting diode (OLED) structure by depositing bis [$N,N '$-(1-naphthyl)-$N,N '$-phenyl] benzidine ($alpha$-NPD) and tris (8-hydroxyquinolinato) aluminum (Alq$_{3}$), respectively, on indium-tin-oxide (ITO) as anode and aluminum (Al) as cathode by the vacuum evaporation deposition using intersecting metal shadow masks. This deposition technique enables us to fabricate four different areas in the same substrate. The crossover area of the deposited thin films were measured by the DFM/KFM, the energy band diagrams were depicted and we considered that the charge behavior of the organic semiconductor depended on the material and the structure.

Communication costs have become a performance bottleneck in many applications, and are a big issue for high performance computing on massively parallel machines. This paper proposes a halo exchange method for unstructured sparse matrix vector products within the algebraic multigrid method, and evaluate it on a supercomputer with mesh/torus networks. In our numerical tests with a Poisson problem, the proposed method accelerates the linear solver more than 14 times with 23040 cores.