NAND-based block devices such as memory cards and solid-state drives embed a flash translation layer (FTL) to emulate the standard block device interface and its features. The overall performance of these devices is determined mainly by the efficiency of the FTL scheme, so intensive research has been performed to improve the average performance of the FTL scheme. However, its worst-case performance has rarely been considered. The present study aims to improve the worst-case performance without affecting the average performance. The central concept is to distribute the garbage collection cost, which is the main source of performance fluctuations, over multiple requests. The proposed scheme comprises three modules: i) anticipated partial log block merging to distribute the garbage collection time; ii) reclaiming clean pages by moving valid pages to bound the worst-case garbage collection time, instead of performing repeated block merges; and iii) victim selection based on the valid page count in a victim log and the required clean page count to avoid subsequent garbage collections. A trace-driven simulation showed that the worst-case performance was improved up to 1,300% using the proposed garbage collection scheme. The average performance was also similar to that of the original scheme. This improvement was achieved without additional memory overheads.

NAND flash storage devices, such as eMMCs and microSD cards, are now widely used in mobile devices. In this paper, we propose a novel buffer replacement scheme for mobile NAND flash storages. It efficiently improves write performance by evicting pages flash-friendly and maintains high cache hit ratios by managing pages in order of recency. Our experimental results show that the proposed scheme outperforms the best performing scheme in the recent literature, Sp.Clock, by 48%.

The objective of this research is to design a high-performance NAND flash memory system with a data buffer. The proposed buffer system in the NAND flash memory consists of two parts, i.e., a fully associative temporal buffer for temporal locality and a fully associative spatial buffer for spatial locality. We propose a new operating mechanism for reducing overhead of flash memory, that is, erase and write operations. According to our simulation results, the proposed buffer system can reduce the write and erase operations by about 73% and 79% for spec application respectively, compared with a fully associative buffer with two times more space. Futhermore, the average memory access time can improve by about 60% compared with other large buffer systems.

NAND Flash memories are widely used as data storages today. The memories are not intrinsically error free because they are affected by several physical disturbances. Technology scaling and introduction of multi-level cell (MLC) has improved data density, but it has made error effect more significant. Error control codes (ECC) are essential to improve reliability of NAND Flash memories. Efficiency of codes depends on error characteristic of systems, and codes are required to be designed to reflect this characteristic. In MLC Flash memories, errors tend to direct values to neighborhood. These errors are a class of M-ary asymmetric symbol error. Some codes which reflect the asymmetric property were proposed. They are designed to correct only 1 level shift errors because almost all of the errors in the memories are in such errors. But technology scaling, increase of program/erase (P/E) cycles, and MLC storing the large number of bits can cause multiple-level shift. This paper proposes single error control codes which can correct an error of more than 1 levels shift. Because the number of levels to be corrected is selectable, we can fit it into noise magnitude. Furthermore, it is possible to add error detecting function for error of the larger shift. Proposed codes are equivalent to a conventional integer codes, which can correct 1 level shift, on a certain parameter. Therefore, the codes are said to be generalization of conventional integer codes. Evaluation results show information lengths to respective check symbol lengths are larger than nonbinary Hamming codes and other M-ary asymmetric symbol error correcting codes.

Recently, the 3-D vertical Floating Gate (FG) type NAND cell arrays with the Sidewall Control Gate (SCG), such as ESCG, DC-SF and S-SCG, are receiving attention to overcome the reliability issues of Charge Trap (CT) type device. Using this novel cell structure, highly reliable flash cell operations were successfully implemented without interference effect on the FG type cell. However, the 3-D vertical FG type cell has large cell size by about 60% for the cylindrical FG structure. In this point of view, we intensively investigate the scalability of the FG width of the 3-D vertical FG NAND cells. In case of the planar FG type NAND cell, the FG height cannot be scaled down due to the necessity of obtaining sufficient coupling ratio and high program speed. In contrast, for the 3-D vertical FG NAND with SCG, the FG is formed cylindrically, which is fully covered with surrounded CG, and very high CG coupling ratio can be achieved. As results, the scaling of FG width of the 3-D vertical FG NAND cell with S-SCG can be successfully demonstrated at 10 nm regime, which is almost the same as the CT layer of recent BE-SONOS NAND.

We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.

Initialize and weak-program erasing scheme is proposed to achieve high-performance and high-reliability Ferroelectric (Fe-) NAND flash solid-state drive (SSD). Bit-by-bit erase VTH control is achieved by the proposed erasing scheme and history effects in Fe-NAND is also suppressed. History effects change the future erase VTH shift characteristics by the past program voltage. The proposed erasing scheme decreases VTH shift variation due to history effects from ±40% to ±2% and the erase VTH distribution width is reduced from over 0.4 V to 0.045 V. As a result, the read and VPASS disturbance decrease by 42% and 37%, respectively. The proposed erasing scheme is immune to VTH variations and voltage stress. The proposed erasing scheme also suppresses the power and bandwidth degradation of SSD.

Recently, the 3-dimensional (3-D) vertical Floating Gate (FG) type NAND flash memory cell arrays with the Extended Sidewall Control Gate (ESCG) was proposed [7]. Using this novel structure, we successfully implemented superior program speed, read current, and less interference characteristics, by the high Control Gate (CG) coupling ratio with less interference capacitance and highly electrical inverted S/D technique. However, the process stability of the ESCG structure has not been sufficiently confirmed such as the variations of the physical dimensions. In this paper, we intensively investigated the electrical dependency according to the physical dimensions of ESCG, such as the line and spacing of ESCG and the thickness of barrier oxide. Using the 2-dimentional (2-D) TCAD simulations, we compared the basic characteristics of the FG type flash cell operation, in the aspect of program speed, read current, and interference effect. Finally, we check the process window and suggest the optimum target of the ESCG structure for reliable flash cell operation. From above all, we confirmed that this 3-dimensional vertical FG NAND flash memory cell arrays using the ESCG structure is the most attractive candidate for terabit 3-D vertical NAND flash cell array.

This paper presents an improvement of the memory cell reliability by the memory cell VTH optimization of the ferroelectric (Fe)-NAND flash memory. The effects of the memory cell VTH on the reliability of the Fe-NAND flash memory are experimentally analyzed for the first time. The reliability is evaluated by the measured VTH shift due to the read disturb, program disturb and data retention. Three types of Fe-NAND flash memory cells, a positive, zero and negative VTH memory cell, are defined on the basis of the memory cell VTH. The middle of VTH of programmed and erased states is 1 V, 0 V and -0.3 V in a positive, zero and negative VTH memory cell, respectively. The VTH shift of the positive, zero and negative VTH memory cells show similar characteristics in the program/erase and the VPASS and VPGM disturbs because the external electric field is so high that the internal depolarization field does not affect the VTH shift. On the other hand, in the data retention, the VTH shift of the three types of VTH memory cells show different characteristics. The reliability of the Fe-NAND flash memory is best optimized in the zero VTH memory cell. In the proposed zero VTH Fe-NAND flash memory cell scheme, the measured VTH shift due to the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively, compared with conventional positive VTH Fe-NAND flash memory cell scheme. Contrarily, in the negative VTH memory cell, the VTH shift during the data retention is 0.49 V and unacceptably large because of the depolarization field. The conventional positive VTH memory cell suffers from a sever read and program disturb. The measured results are drastically different from those of the conventional floating-gate NAND flash memory cell where the negative VTH memory cell is most suitable in terms of the reliability.

In disk-based storage systems, non-volatile write caches have been widely used to reduce write latency as well as to ensure data consistency at the level of a storage controller. Write cache policies should basically consider which data is important to cache and evict, and they should also take into account the real I/O features of a non-volatile device. However, existing work has mainly focused on improving basic cache operations, but has not considered the I/O cost of a non-volatile device properly. In this paper, we propose a pattern-aware write cache policy, PAW for a NAND flash memory in disk-based mobile storage systems. PAW is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. In addition, PAW employs the synergistic effect of combining a pattern-aware write cache policy and an I/O clustering-based queuing method to strengthen the sequentiality with the aim of reducing the overall system I/O latency. For evaluations, we have built a practical hard disk simulator with a non-volatile cache of a NAND flash memory. Experimental results show that our policy significantly improves the overall I/O performance by reducing the overhead from a non-volatile cache considerably over a traditional one, achieving a high efficiency in energy consumption.

This letter introduces a buffer management issue in designing SSDs for log-structured file systems (LFSs). We implemented a novel trace-driven SSD simulator in SystemC language, and simulated several SSD architectures with the NILFS2 trace. From the results, we give two major considerations related to the buffer management as follows. (1) The write buffer is used as a buffer not a cache, since all write requests are sequential in NILFS2. (2) For better performance, the main architectural factor is the bus bandwidth, but 332 MHz is enough. Instead, the read buffer makes a key role in performance improvement while caching data. To enhance SSDs, accordingly, it is an effective way to make efficient read buffer management policies, and one of the examples is tracking the valid data zone in NILFS2, which can increase the data hit ratio in read buffers significantly.

The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.

A new low voltage operation of high voltage switching technique, which is capable of reducing leakage current by an order of three compared to conventional circuits, has been developed for sub-1.8 V low voltage mobile NAND flash memory. In addition, by using the proposed high voltage switch, chip size scaling can be realized due to reduced a minimum required space between the N-wells of selected and unselected blocks for isolation. The proposed scheme is essential to achieve low power operation NAND Flash memory, especially for mobile electronics.

We propose an efficient dynamic hash index structure suitable for a NAND flash memory environment. Since write operations incur significant overhead in NAND flash memory, our design of index structure focuses on minimizing the number of write operations for hash index updates. Through a set of extensive experiments, we show the effectiveness of the proposed hash index structure in a NAND flash memory environment.

We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process. We can make NAND flash memory with 3F2 cell size. Using SILVACO ATLAS simulation, we study terraced NAND flash memory characteristics such as program, erase, and read. Also, its fabrication method is proposed.

In this paper, we present an efficient index structure for NAND flash memory, called the Dynamic Forest (D-Forest). Since write operations incur high overhead on NAND flash memory, D-Forest is designed to minimize write operations for index updates. The experimental results show that D-Forest significantly reduces write operations compared to the conventional B+-tree.

Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4],[5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.

We propose a Solid-State Disk (SSD) with a Double Data Rate (DDR) DRAM interface for high-performance PCs. Traditional SSDs simply inherit the interface protocol of Hard Disk Drives (HDD) such as Parallel Advanced Technology Attachment (PATA) or Serial-ATA (SATA) for maintaining the compatibility. However, SSD itself provides much higher performance than HDD, hence the interface also needs to be enhanced. Unlike the traditional SSDs, the proposed SSD with DDR DRAM interface is placed in the North Bridge which provides two or more DDR DRAM interface ports in high-performance PCs. The novelty of our work is on DQS signaling scheme which allows arbitrary Column Address Strobe (CAS) latency unlike typical DDR DRAM interface scheme. The experimental results show that the proposed SSD maximally outperforms the traditional SSD by 8.7 times in read mode, by 1.5 times in write mode. Also, for synthetic workloads, the proposed scheme shows performance improvement over the conventional architecture by a factor of 1.6 times.

We propose a universal NAND logic gate based on single flux quantum (SFQ) logic. The NAND gate enables the construction of any logic circuits. In the proposed gate, three superconducting loops share two Josephson junctions (JJs). The critical currents of the JJs were designed to allow each of any two loops to trap an SFQ at the same time. We simulated dynamic operation of this NAND gate. The results show that the NAND gate can operate with a delay time of 45 ps, and the power consumption of this circuit is close to 0.06 µW/gate.