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[Keyword] OMP(3945hit)

1721-1740hit(3945hit)

  • Characterization of Left-Handed Traveling-Wave Transistors

    Shun NAKAGAWA  Koichi NARAHARA  

     
    PAPER-Microwaves, Millimeter-Waves

      Vol:
    E92-C No:11
      Page(s):
    1396-1400

    The characteristics of a left-handed traveling-wave transistor, which is formulated as two composite right- and left-handed (CRLH) transmission lines with both passive and active couplings, are discussed for generating unattenuated waves having left-handedness. The design criteria for convective instability are described, together with results of numerical calculations that solve the transmission equation for the device.

  • Improvement of Mode Distribution in a Triangular Prism Reverberation Chamber by QRS Diffuser

    Eugene RHEE  Joong-Geun RHEE  

     
    PAPER-Electromagnetic Compatibility(EMC)

      Vol:
    E92-B No:11
      Page(s):
    3478-3483

    This paper presents the field uniformity characteristics in a triangular prism reverberation chamber that can be substituted for an open area test site or an anechoic chamber to measure electromagnetic interference. To improve size problems of a stirrer that is an official unit to generate a uniform field in the reverberation chamber, we suggest a diffuser of Quadratic Residue Sequence method. To validate the substitution of a diffuser for a stirrer, a diffuser is designed for 1-3 GHz, and three types of equilateral triangular prism reverberation chambers are modeled. Afterwards, the field distributions in these three reverberation chambers are both simulated and tested. Using XFDTD 6.2 of finite difference time domain method, field deviations of each structure are simulated and compared to each other. An evaluation of field uniformity is done by cumulative probability distribution which is specified in the IEC 61000-4-21. The result shows that the field uniformity in the chamber is within 6 dB tolerance and also within 3 dB standard deviation, which means a diffuser can satisfy the requirement of international standards.

  • OTHR Impulsive Interference Suppression in Strong Clutter Background

    Tao LIU  Yu GONG  Yaohuan GONG  

     
    PAPER-Digital Signal Processing

      Vol:
    E92-A No:11
      Page(s):
    2866-2873

    External interferences can severely degrade the performance of an Over-the-horizon radar (OTHR), so suppression of external interferences in strong clutter environment is the prerequisite for the target detection. The traditional suppression solutions usually began with clutter suppression in either time or frequency domain, followed by the interference detection and suppression. Based on this traditional solution, this paper proposes a method characterized by joint clutter suppression and interference detection: by analyzing eigenvalues in a short-time moving window centered at different time position, clutter is suppressed by discarding the maximum three eigenvalues at every time position and meanwhile detection is achieved by analyzing the remained eigenvalues at different position. Then, restoration is achieved by forward-backward linear prediction using interference-free data surrounding the interference position. In the numeric computation, the eigenvalue decomposition (EVD) is replaced by singular values decomposition (SVD) based on the equivalence of these two processing. Data processing and experimental results show its efficiency of noise floor falling down about 10-20 dB.

  • Computational Complexity of Liveness Problem of Normal Petri Net

    Atsushi OHTA  Kohkichi TSUJI  

     
    PAPER

      Vol:
    E92-A No:11
      Page(s):
    2717-2722

    Petri net is a powerful modeling tool for concurrent systems. Liveness, which is a problem to verify there exists no local deadlock, is one of the most important properties of Petri net to analyze. Computational complexity of liveness of a general Petri net is deterministic exponential space. Liveness is studied for subclasses of Petri nets to obtain necessary and sufficient conditions that need less computational cost. These are mainly done using a subset of places called siphons. CS-property, which denotes that every siphon has token(s) in every reachable marking, in one of key properties in liveness analysis. On the other hand, normal Petri net is a subclass of Petri net whose reachability set can be effectively calculated. This paper studies computational complexity of liveness problem of normal Petri nets. First, it is shown that liveness of a normal Petri net is equivalent to cs-property. Then we show this problem is co-NP complete by deriving a nondeterministic algorithm for non-liveness which is similar to the algorithm for liveness suggested by Howell et al. Lastly, we study structural feature of bounded Petri net where liveness and cs-property are equivalent. From this consideration, liveness problem of bounded normal Petri net is shown to be deterministic polynomial time complexity.

  • Shift-Invariant Sparse Image Representations Using Tree-Structured Dictionaries

    Makoto NAKASHIZUKA  Hidenari NISHIURA  Youji IIGUNI  

     
    PAPER-Image Processing

      Vol:
    E92-A No:11
      Page(s):
    2809-2818

    In this study, we introduce shift-invariant sparse image representations using tree-structured dictionaries. Sparse coding is a generative signal model that approximates signals by the linear combinations of atoms in a dictionary. Since a sparsity penalty is introduced during signal approximation and dictionary learning, the dictionary represents the primal structures of the signals. Under the shift-invariance constraint, the dictionary comprises translated structuring elements (SEs). The computational cost and number of atoms in the dictionary increase along with the increasing number of SEs. In this paper, we propose an algorithm for shift-invariant sparse image representation, in which SEs are learnt with a tree-structured approach. By using a tree-structured dictionary, we can reduce the computational cost of the image decomposition to the logarithmic order of the number of SEs. We also present the results of our experiments on the SE learning and the use of our algorithm in image recovery applications.

  • A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs

    Guy TORFS  Zhisheng LI  Johan BAUWELINCK  Xin YIN  Jan VANDEWEGE  Geert Van Der PLAS  

     
    LETTER-Electronic Components

      Vol:
    E92-C No:10
      Page(s):
    1328-1330

    A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 µW at 1.8 V power supply and 1 GHz clock frequency.

  • Near-Optimal Auto-Configuration of PCID in LTE Cellular Systems

    Navrati SAXENA  Abhishek ROY  Jeong Jae WON  

     
    LETTER-Network

      Vol:
    E92-B No:10
      Page(s):
    3252-3255

    In this letter we show that the dynamic optimal PCID allocation problem in LTE systems is NP-complete. Subsequently we provide a near-optimal solution using SON which models the problem using new merge operations and explores the search space using a suitable randomized algorithmic approach. Two feasible options for dynamic auto-configuration of the system are also discussed. Simulation results point out that the approach provides near-optimal auto-configuration of PCIDs in computationally feasible time.

  • Synthesis and Design of Parameter Extractors for Low-Power Pre-Computation-Based Content-Addressable Memory

    Shanq-Jang RUAN  Jui-Yuan HSIEH  Chia-Han LEE  

     
    PAPER

      Vol:
    E92-C No:10
      Page(s):
    1249-1257

    This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.

  • Compiler Framework for Reconfigurable Computing Architecture

    Chongyong YIN  Shouyi YIN  Leibo LIU  Shaojun WEI  

     
    BRIEF PAPER

      Vol:
    E92-C No:10
      Page(s):
    1284-1290

    Compiler is the most important supporting tool to facilitate the use of reconfigurable computing architecture (RCA). In this paper, a template-based compiler framework is proposed. This compiler can synthesize the executables for RCA from native high-level programming language source code directly. It supports to generate run-time dynamic configuration context. And it is capable to generate both full configuration context and partial configuration context. Experimental results show that the executables generated by the proposed compiler can achieve better execution performance and smaller configuration context size than previous compilers. Moreover, this compiler does not require the programmer to have any extra knowledge about the hardware architecture of RCA.

  • A Novel Robust Impulsive Chaos Synchronization Approach for Uncertain Complex Dynamical Networks

    Nariman MAHDAVI MAZDEH  Mohammad Bagher MENHAJ  Heidar Ali TALEBI  

     
    PAPER-Nonlinear Problems

      Vol:
    E92-A No:10
      Page(s):
    2499-2507

    This paper presents a novel approach for robust impulsive synchronization of uncertain complex dynamical networks, each node of which possesses chaotic dynamics with different parameters perturbation and external disturbances as well as unknown but bounded network coupling effects. A new sufficient condition is proposed that guarantees the global robust synchronizing of such a network. Finally, the effectiveness of the proposed approach is evaluated by performing simulations on two illustrative examples.

  • Efficient Compression of Web Graphs

    Yasuhito ASANO  Yuya MIYAWAKI  Takao NISHIZEKI  

     
    PAPER-Data Compression

      Vol:
    E92-A No:10
      Page(s):
    2454-2462

    Several methods have been proposed for compressing the linkage data of a Web graph. Among them, the method proposed by Boldi and Vigna is known as the most efficient one. In the paper, we propose a new method to compress a Web graph. Our method is more efficient than theirs with respect to the size of the compressed data. For example, our method needs only 1.99 bits per link to compress a Web graph containing 3,216,152 links connecting 325,557 pages, while the method of Boldi and Vigna needs 2.84 bits per link to compress the same Web graph.

  • Static Dependency Pair Method Based on Strong Computability for Higher-Order Rewrite Systems

    Keiichirou KUSAKARI  Yasuo ISOGAI  Masahiko SAKAI  Frederic BLANQUI  

     
    PAPER-Computation and Computational Models

      Vol:
    E92-D No:10
      Page(s):
    2007-2015

    Higher-order rewrite systems (HRSs) and simply-typed term rewriting systems (STRSs) are computational models of functional programs. We recently proposed an extremely powerful method, the static dependency pair method, which is based on the notion of strong computability, in order to prove termination in STRSs. In this paper, we extend the method to HRSs. Since HRSs include λ-abstraction but STRSs do not, we restructure the static dependency pair method to allow λ-abstraction, and show that the static dependency pair method also works well on HRSs without new restrictions.

  • A Decentralized VPN Service over Generalized Mobile Ad-Hoc Networks

    Sho FUJITA  Keiichi SHIMA  Yojiro UO  Hiroshi ESAKI  

     
    PAPER-Network Architecture and Testbed

      Vol:
    E92-D No:10
      Page(s):
    1897-1904

    We present a decentralized VPN service that can be built over generalized mobile ad-hoc networks (Generalized MANETs), in which topologies can be represented as a time-varying directed multigraph. We address wireless ad-hoc networks and overlay ad-hoc networks as instances of Generalized MANETs. We first propose an architecture to operate on various kinds of networks through a single set of operations. Then, we design and implement a decentralized VPN service on the proposed architecture. Through the development and operation of a prototype system we implemented, we found that the proposed architecture makes the VPN service applicable to each instance of Generalized MANETs, and that the VPN service makes it possible for unmodified applications to operate on the networks.

  • Estimating Node Characteristics from Topological Structure of Social Networks

    Kouhei SUGIYAMA  Hiroyuki OHSAKI  Makoto IMASE  

     
    PAPER-Fundamental Theories for Communications

      Vol:
    E92-B No:10
      Page(s):
    3094-3101

    In this paper, for systematically evaluating estimation methods of node characteristics, we first propose a social network generation model called LRE (Linkage with Relative Evaluation). LRE is a network generation model, which aims to reproduce the characteristics of a social network. LRE utilizes the fact that people generally build relationships with others based on relative evaluation, rather than absolute evaluation. We then extensively evaluate the accuracy of the estimation method called SSI (Structural Superiority Index). We reveal that SSI is effective for finding good nodes (e.g., top 10% nodes), but cannot be used for finding excellent nodes (e.g., top 1% nodes). For alleviating the problems of SSI, we propose a novel scheme for enhancing existing estimation methods called RENC (Recursive Estimation of Node Characteristic). RENC reduces the effect of noise by recursively estimating node characteristics. By investigating the estimation accuracy with RENC, we show that RENC is quite effective for improving the estimation accuracy in practical situations.

  • Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes

    Hironori UCHIKAWA  Kohsuke HARADA  

     
    PAPER-Coding Theory

      Vol:
    E92-A No:10
      Page(s):
    2411-2417

    We propose a complexity-reducing algorithm for serial scheduled min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed algorithm is evaluated by computer simulations and shown to reduce the decoding complexity about 20% compared with a conventional serial scheduled min-sum decoding with small fractional decibel degradation in error correction performance.

  • Construction and Design Equations of a Lumped Element Dual-Band Wilkinson Divider

    Takeshi OSHIMA  Masataka OHTSUKA  Hiroaki MIYASHITA  Yoshihiko KONISHI  

     
    LETTER-Microwaves, Millimeter-Waves

      Vol:
    E92-C No:10
      Page(s):
    1322-1324

    This letter presents the construction and design equations of a lumped element Wilkinson divider with dual-band operation. This divider is constructed of series and parallel LC resonant circuits, and an isolation resistor. The element values can be uniquely determined by giving the two frequencies for operation as a Wilkinson divider and the load resistance. An 800 MHz/2 GHz dual-band Wilkinson divider is treated as a design example, and its operation is verified by simulation and experiment. The fabricated divider has compact dimensions of 3.564 mm2.

  • An Inter-Cell Interference Mitigation Method for OFDM-Based Cellular Systems Using Independent Component Analysis

    Hui ZHANG  Xiaodong XU  Xiaofeng TAO  Ping ZHANG  Ping WU  

     
    PAPER

      Vol:
    E92-B No:10
      Page(s):
    3034-3042

    Orthogonal frequency division multiplexing (OFDM) is a critical technology in 3G evolution systems, which can effectively avoid intra-cell interference, but may bring with serious inter-cell interference. Inter-cell interference cancellation is one of effective schemes taken in mitigating inter-cell interference, but for many existing schemes in inter-cell interference cancellation, various generalized spatial diversities are taken, which always bring with extra interference and blind spots, or even need to acquire extra information on source and channel. In this paper, a novel inter-cell interference mitigation method is proposed for 3G evolution systems. This method is based on independent component analysis in blind source separation, and the input signal to interference plus noise ratio (SINR) is set as objective function. By generalized eigenvalue decomposition and algorithm iterations, maximum signal noise ratio (SNR) can be obtained in output. On the other hand, this method can be worked with no precise knowledge of source signal and channel information. Performance evaluation shows that such method can mitigate inter-cell interference in a semi-blind state, and effectively improve output SNR with the condition that lower input SINR, higher input SNR and longer lengths of the processing frame.

  • Code Compression with Split Echo Instructions

    Iver STUBDAL  Arda KARADUMAN  Hideharu AMANO  

     
    PAPER-Fundamentals of Software and Theory of Programs

      Vol:
    E92-D No:9
      Page(s):
    1650-1656

    Code density is often a critical issue in embedded computers, since the memory size of embedded systems is strictly limited. Echo instructions have been proposed as a method for reducing code size. This paper presents a new type of echo instruction, split echo, and evaluates an implementation of both split echo and traditional echo instructions on a MIPS R3000 based processor. Evaluation results show that memory requirement is reduced by 12% on average with small additional hardware cost.

  • Wide-Band Dispersion Compensation for PCF with Uniform Air Hole Structure

    Kazuhide NAKAJIMA  Takashi MATSUI  Chisato FUKAI  

     
    LETTER-Optical Fiber for Communications

      Vol:
    E92-B No:9
      Page(s):
    2951-2953

    We investigate numerically the applicability of photonic crystal fiber (PCF) with a uniform air hole structure as a wide-band transmission medium. We show that accumulated dispersion over the PCF can be reduced effectively by optimizing the index profile of dispersion compensating fiber (DCF). We also show that a bandwidth of more than 300 nm will be available for 40 Gbit/s NRZ transmission by using the PCF as a transmission medium instead of conventional 1.3 µm zero-dispersion single-mode fiber (SMF).

  • Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n -1, 2n+1 -1} and {22n, 2n -1, 2n-1 -1}

    Amir Sabbagh MOLAHOSSEINI  Chitra DADKHAH  Keivan NAVI  Mohammad ESHGHI  

     
    PAPER-Computer Systems

      Vol:
    E92-D No:9
      Page(s):
    1628-1638

    In this paper, the new residue number system (RNS) moduli sets {22n, 2n -1, 2n+1 -1} and {22n, 2n -1, 2n-1 -1} are introduced. These moduli sets have 4n-bit dynamic range and well-formed moduli which can result in high-performance residue to binary converters as well as efficient RNS arithmetic unit. Next, efficient residue to binary converters for the proposed moduli sets based on mixed-radix conversion (MRC) algorithm are presented. The converters are ROM-free and they are realized using carry-save adders and modulo adders. Comparison with the other residue to binary converters for 4n-bit dynamic range moduli sets shown that the presented designs based on new moduli sets {22n, 2n -1, 2n+1 -1} and {22n, 2n -1, 2n-1 -1} are improved the conversion delay and result in hardware savings. Also, the proposed moduli sets can lead to efficient binary to residue converters, and they can speed-up internal RNS arithmetic processing, compared with the other 4n-bit dynamic range moduli sets.

1721-1740hit(3945hit)